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Fix address mode 3 immediate offset mode encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59109 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -736,11 +736,11 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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// Set bit[3:0] to the corresponding Rm register
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Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
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// if this instr is in scaled register offset/index instruction, set
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// If this instr is in scaled register offset/index instruction, set
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// shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
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if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
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Binary |= getShiftOp(AM2Opc) << 5; // shift
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Binary |= ShImm << 7; // shift_immed
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Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
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Binary |= ShImm << ARMII::ShiftShift; // shift_immed
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}
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emitWordLE(Binary);
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@ -792,8 +792,8 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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Binary |= 1 << ARMII::AM3_I_BitShift;
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
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// Set operands
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Binary |= (ImmOffs >> 4) << 8; // immedH
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Binary |= (ImmOffs & ~0xF); // immedL
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Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
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Binary |= (ImmOffs & 0xF); // immedL
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}
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emitWordLE(Binary);
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@ -116,8 +116,10 @@ namespace ARMII {
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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M_BitShift = 5,
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ShiftImmShift = 5,
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ShiftShift = 7,
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N_BitShift = 7,
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ImmHiShift = 8,
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SoRotImmShift = 8,
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RegRsShift = 8,
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ExtRotImmShift = 10,
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