RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-02 00:37:09 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

CXX TLS: collect return blocks after SelectAllBasicBlocks.

Browse Source 
It is incorrect to get the corresponding MBB for a ReturnInst before
SelectAllBasicBlocks since SelectAllBasicBlocks can change the
correspondence between a ReturnInst and the MBB it is in.

PR27062


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren 2016-03-24 23:21:29 +00:00
parent 79b059889d
commit 7121713797
2 changed files with 31 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -469,7 +469,6 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
MF->setHasInlineAsm(false);
FuncInfo->SplitCSR = false;
SmallVector<MachineBasicBlock*, 4> Returns;
// We split CSR if the target supports it for the given function
// and the function has only return exits.
@ -482,12 +481,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
continue;
const TerminatorInst *Term = BB.getTerminator();
if (isa<UnreachableInst>(Term))
if (isa<UnreachableInst>(Term) || isa<ReturnInst>(Term))
continue;
if (isa<ReturnInst>(Term)) {
Returns.push_back(FuncInfo->MBBMap[&BB]);
continue;
}
// Bail out if the exit block is not Return nor Unreachable.
FuncInfo->SplitCSR = false;
@ -509,8 +504,21 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
// Insert copies in the entry block and the return blocks.
if (FuncInfo->SplitCSR)
if (FuncInfo->SplitCSR) {
SmallVector<MachineBasicBlock*, 4> Returns;
// Collect all the return blocks.
for (MachineBasicBlock &MBB : mf) {
if (!MBB.succ_empty())
continue;
MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
if (Term != MBB.end() && Term->isReturn()) {
Returns.push_back(&MBB);
continue;
}
}
TLI->insertCopiesSplitCSR(EntryMBB, Returns);
}
DenseMap<unsigned, unsigned> LiveInMap;
if (!FuncInfo->ArgDbgValues.empty())

16
test/CodeGen/X86/cxx_tlscc64.ll
View File

@ -151,5 +151,21 @@ entry:
ret void
}
@ssp_var = internal thread_local global i8 0, align 1
; CHECK-LABEL: test_ssp
; CHECK-NOT: pushq %r11
; CHECK-NOT: pushq %r10
; CHECK-NOT: pushq %r9
; CHECK-NOT: pushq %r8
; CHECK-NOT: pushq %rsi
; CHECK-NOT: pushq %rdx
; CHECK-NOT: pushq %rcx
; CHECK-NOT: pushq %rbx
; CHECK: callq
define cxx_fast_tlscc nonnull i8* @test_ssp() #2 {
ret i8* @ssp_var
}
attributes #0 = { nounwind "no-frame-pointer-elim"="true" }
attributes #1 = { nounwind }
attributes #2 = { nounwind sspreq }