allow a virtual register to be associated with live-in values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21927 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-05-13 07:08:07 +00:00
parent fe07581d78
commit 712ad0c36d
3 changed files with 22 additions and 15 deletions

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@ -108,7 +108,10 @@ class MachineFunction : private Annotation {
/// LiveIns/LiveOuts - Keep track of the physical registers that are /// LiveIns/LiveOuts - Keep track of the physical registers that are
/// livein/liveout of the function. Live in values are typically arguments in /// livein/liveout of the function. Live in values are typically arguments in
/// registers, live out values are typically return values in registers. /// registers, live out values are typically return values in registers.
std::vector<unsigned> LiveIns, LiveOuts; /// LiveIn values are allowed to have virtual registers associated with them,
/// stored in the second element.
std::vector<std::pair<unsigned, unsigned> > LiveIns;
std::vector<unsigned> LiveOuts;
public: public:
MachineFunction(const Function *Fn, const TargetMachine &TM); MachineFunction(const Function *Fn, const TargetMachine &TM);
@ -177,16 +180,20 @@ public:
/// addLiveIn/Out - Add the specified register as a live in/out. Note that it /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
/// is an error to add the same register to the same set more than once. /// is an error to add the same register to the same set more than once.
void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } void addLiveIn(unsigned Reg, unsigned vreg = 0) {
LiveIns.push_back(std::make_pair(Reg, vreg));
}
void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
// Iteration support for live in/out sets. These sets are kept in sorted // Iteration support for live in/out sets. These sets are kept in sorted
// order by their register number. // order by their register number.
typedef std::vector<unsigned>::const_iterator liveinout_iterator; typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
liveinout_iterator livein_begin() const { return LiveIns.begin(); } livein_iterator;
liveinout_iterator livein_end() const { return LiveIns.end(); } typedef std::vector<unsigned>::const_iterator liveout_iterator;
liveinout_iterator liveout_begin() const { return LiveOuts.begin(); } livein_iterator livein_begin() const { return LiveIns.begin(); }
liveinout_iterator liveout_end() const { return LiveOuts.end(); } livein_iterator livein_end() const { return LiveIns.end(); }
liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
liveout_iterator liveout_end() const { return LiveOuts.end(); }
/// getBlockNumbered - MachineBasicBlocks are automatically numbered when they /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they
/// are inserted into the machine function. The block number for a machine /// are inserted into the machine function. The block number for a machine

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@ -95,7 +95,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// beginning of the function that we will pretend "defines" the values. This // beginning of the function that we will pretend "defines" the values. This
// is to make the interval analysis simpler by providing a number. // is to make the interval analysis simpler by providing a number.
if (fn.livein_begin() != fn.livein_end()) { if (fn.livein_begin() != fn.livein_end()) {
unsigned FirstLiveIn = *fn.livein_begin(); unsigned FirstLiveIn = fn.livein_begin()->first;
// Find a reg class that contains this live in. // Find a reg class that contains this live in.
const TargetRegisterClass *RC = 0; const TargetRegisterClass *RC = 0;
@ -128,11 +128,11 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// Note intervals due to live-in values. // Note intervals due to live-in values.
if (fn.livein_begin() != fn.livein_end()) { if (fn.livein_begin() != fn.livein_end()) {
MachineBasicBlock *Entry = fn.begin(); MachineBasicBlock *Entry = fn.begin();
for (MachineFunction::liveinout_iterator I = fn.livein_begin(), for (MachineFunction::livein_iterator I = fn.livein_begin(),
E = fn.livein_end(); I != E; ++I) { E = fn.livein_end(); I != E; ++I) {
handlePhysicalRegisterDef(Entry, Entry->begin(), handlePhysicalRegisterDef(Entry, Entry->begin(),
getOrCreateInterval(*I), 0, 0); getOrCreateInterval(I->first), 0, 0);
for (const unsigned* AS = mri_->getAliasSet(*I); *AS; ++AS) for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
handlePhysicalRegisterDef(Entry, Entry->begin(), handlePhysicalRegisterDef(Entry, Entry->begin(),
getOrCreateInterval(*AS), 0, 0); getOrCreateInterval(*AS), 0, 0);
} }

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@ -165,11 +165,11 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
VirtRegInfo.resize(64); VirtRegInfo.resize(64);
// Mark live-in registers as live-in. // Mark live-in registers as live-in.
for (MachineFunction::liveinout_iterator I = MF.livein_begin(), for (MachineFunction::livein_iterator I = MF.livein_begin(),
E = MF.livein_end(); I != E; ++I) { E = MF.livein_end(); I != E; ++I) {
assert(MRegisterInfo::isPhysicalRegister(*I) && assert(MRegisterInfo::isPhysicalRegister(I->first) &&
"Cannot have a live-in virtual register!"); "Cannot have a live-in virtual register!");
HandlePhysRegDef(*I, 0); HandlePhysRegDef(I->first, 0);
} }
// Calculate live variable information in depth first order on the CFG of the // Calculate live variable information in depth first order on the CFG of the
@ -272,7 +272,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// it as using all of the live-out values in the function. // it as using all of the live-out values in the function.
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
MachineInstr *Ret = &MBB->back(); MachineInstr *Ret = &MBB->back();
for (MachineFunction::liveinout_iterator I = MF.liveout_begin(), for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
E = MF.liveout_end(); I != E; ++I) { E = MF.liveout_end(); I != E; ++I) {
assert(MRegisterInfo::isPhysicalRegister(*I) && assert(MRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!"); "Cannot have a live-in virtual register!");