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Do not generate a FP_ROUND of f64 to f64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46195 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2008-01-20 01:18:38 +00:00
parent 187784996c
commit 713ed3f7c0
1 changed files with 4 additions and 3 deletions
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7
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3608,10 +3608,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
if (SrcVT == MVT::ppcf128) {
SDOperand Lo, Hi;
ExpandOp(Node->getOperand(0), Lo, Hi);
SDOperand Lo;
ExpandOp(Node->getOperand(0), Lo, Result);
// Round it the rest of the way (e.g. to f32) if needed.
Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi, Op.getOperand(1));
if (DstVT!=MVT::f64)
Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
break;
}
// The only other way we can lower this is to turn it into a STORE,