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misched: Remove LoopDependencies heuristic.

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This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-10-09 23:44:23 +00:00
parent 1b005075b6
commit 714973e459
2 changed files with 1 additions and 110 deletions
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70
include/llvm/CodeGen/ScheduleDAGInstrs.h
View File

@ -31,72 +31,6 @@ namespace llvm {
class LiveIntervals;
class RegPressureTracker;
/// LoopDependencies - This class analyzes loop-oriented register
/// dependencies, which are used to guide scheduling decisions.
/// For example, loop induction variable increments should be
/// scheduled as soon as possible after the variable's last use.
///
class LoopDependencies {
const MachineDominatorTree &MDT;
public:
typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
LoopDeps;
LoopDeps Deps;
LoopDependencies(const MachineDominatorTree &mdt) : MDT(mdt) {}
/// VisitLoop - Clear out any previous state and analyze the given loop.
///
void VisitLoop(const MachineLoop *Loop) {
assert(Deps.empty() && "stale loop dependencies");
MachineBasicBlock *Header = Loop->getHeader();
SmallSet<unsigned, 8> LoopLiveIns;
for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
LE = Header->livein_end(); LI != LE; ++LI)
LoopLiveIns.insert(*LI);
const MachineDomTreeNode *Node = MDT.getNode(Header);
const MachineBasicBlock *MBB = Node->getBlock();
assert(Loop->contains(MBB) &&
"Loop does not contain header!");
VisitRegion(Node, MBB, Loop, LoopLiveIns);
}
private:
void VisitRegion(const MachineDomTreeNode *Node,
const MachineBasicBlock *MBB,
const MachineLoop *Loop,
const SmallSet<unsigned, 8> &LoopLiveIns) {
unsigned Count = 0;
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
const MachineInstr *MI = I;
if (MI->isDebugValue())
continue;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
unsigned MOReg = MO.getReg();
if (LoopLiveIns.count(MOReg))
Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
}
++Count; // Not every iteration due to dbg_value above.
}
const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
for (std::vector<MachineDomTreeNode*>::const_iterator I =
Children.begin(), E = Children.end(); I != E; ++I) {
const MachineDomTreeNode *ChildNode = *I;
MachineBasicBlock *ChildBlock = ChildNode->getBlock();
if (Loop->contains(ChildBlock))
VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
}
}
};
/// An individual mapping from virtual register number to SUnit.
struct VReg2SUnit {
unsigned VirtReg;
@ -236,10 +170,6 @@ namespace llvm {
/// to minimize construction/destruction.
std::vector<SUnit *> PendingLoads;
/// LoopRegs - Track which registers are used for loop-carried dependencies.
///
LoopDependencies LoopRegs;
/// DbgValues - Remember instruction that precedes DBG_VALUE.
/// These are generated by buildSchedGraph but persist so they can be
/// referenced when emitting the final schedule.

41
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -46,8 +46,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
LiveIntervals *lis)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
IsPostRA(IsPostRAFlag), CanHandleTerminators(false), LoopRegs(MDT),
FirstDbgValue(0) {
IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) {
assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
@ -138,10 +137,6 @@ static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
BB = bb;
LoopRegs.Deps.clear();
if (MachineLoop *ML = MLI.getLoopFor(BB))
if (BB == ML->getLoopLatch())
LoopRegs.VisitLoop(ML);
}
void ScheduleDAGInstrs::finishBlock() {
@ -318,40 +313,6 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
// retrieve the existing SUnits list for this register's defs.
std::vector<PhysRegSUOper> &DefList = Defs[MO.getReg()];
// If a def is going to wrap back around to the top of the loop,
// backschedule it.
if (DefList.empty()) {
LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(MO.getReg());
if (I != LoopRegs.Deps.end()) {
const MachineOperand *UseMO = I->second.first;
unsigned Count = I->second.second;
const MachineInstr *UseMI = UseMO->getParent();
unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
const MCInstrDesc &UseMCID = UseMI->getDesc();
// TODO: If we knew the total depth of the region here, we could
// handle the case where the whole loop is inside the region but
// is large enough that the isScheduleHigh trick isn't needed.
if (UseMOIdx < UseMCID.getNumOperands()) {
// Currently, we only support scheduling regions consisting of
// single basic blocks. Check to see if the instruction is in
// the same region by checking to see if it has the same parent.
if (UseMI->getParent() != MI->getParent()) {
unsigned Latency = SU->Latency;
// This is a wild guess as to the portion of the latency which
// will be overlapped by work done outside the current
// scheduling region.
Latency -= std::min(Latency, Count);
// Add the artificial edge.
ExitSU.addPred(SDep(SU, SDep::Order, Latency,
/*Reg=*/0, /*isNormalMemory=*/false,
/*isMustAlias=*/false,
/*isArtificial=*/true));
}
}
LoopRegs.Deps.erase(I);
}
}
// clear this register's use list
if (Uses.contains(MO.getReg()))
Uses[MO.getReg()].clear();