RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-28 23:43:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-01-07 05:45:56 +00:00
parent c12979aa1c
commit 71ab7a79a7
4 changed files with 93 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -99,7 +99,7 @@ multiclass ALU32_Pbase<string mnemonic, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : ALU32_rr<(outs IntRegs:$dst),
def NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, $src3)",
@ -108,9 +108,9 @@ multiclass ALU32_Pbase<string mnemonic, bit isNot,
multiclass ALU32_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
}
}
@ -118,7 +118,7 @@ let InputType = "reg" in
multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
let isPredicable = 1 in
def #NAME# : ALU32_rr<(outs IntRegs:$dst),
def NAME : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = "#mnemonic#"($src1, $src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
@ -145,7 +145,7 @@ defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
//===----------------------------------------------------------------------===//
multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : ALU32_ri<(outs IntRegs:$dst),
def NAME : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, #$src3)",
@ -154,9 +154,9 @@ multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
}
}
@ -165,7 +165,7 @@ multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
isPredicable = 1 in
def #NAME# : ALU32_ri<(outs IntRegs:$dst),
def NAME : ALU32_ri<(outs IntRegs:$dst),
(ins IntRegs:$src1, s16Ext:$src2),
"$dst = "#mnemonic#"($src1, #$src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
@ -223,14 +223,14 @@ def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
multiclass TFR_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
def _c#NAME# : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2),
def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
let PNewValue = "new" in
def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2),
def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
}
@ -240,7 +240,7 @@ let InputType = "reg", neverHasSideEffects = 1 in
multiclass TFR_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let isPredicable = 1 in
def #NAME# : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
"$dst = $src1",
[]>;
@ -253,14 +253,14 @@ multiclass TFR_base<string CextOp> {
multiclass TFR64_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
def _c#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
let PNewValue = "new" in
def _cdn#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
def _cdn#NAME : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
}
@ -270,7 +270,7 @@ let InputType = "reg", neverHasSideEffects = 1 in
multiclass TFR64_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let isPredicable = 1 in
def #NAME# : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
def NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
"$dst = $src1",
[]>;
@ -284,15 +284,15 @@ multiclass TFR64_base<string CextOp> {
multiclass TFRI_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
def _c#NAME# : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Ext:$src2),
def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Ext:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
[]>;
// Predicate new
let PNewValue = "new" in
def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Ext:$src2),
def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Ext:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
[]>;
}
@ -303,7 +303,7 @@ multiclass TFRI_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
isReMaterializable = 1 in
def #NAME# : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
"$dst = #$src1",
[(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
@ -846,7 +846,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : LDInst2<(outs RC:$dst),
def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, MEMri:$addr),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($addr)",
@ -855,9 +855,9 @@ multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
}
}
@ -868,7 +868,7 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
def #NAME# : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
"$dst = "#mnemonic#"($addr)",
[]>;
@ -912,8 +912,8 @@ def : Pat < (i64 (load ADDRriS11_3:$addr)),
multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+#$src3)",
[]>;
@ -922,9 +922,9 @@ multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
}
}
@ -936,7 +936,7 @@ multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1, AddedComplexity = 20 in
def #NAME# : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
"$dst = "#mnemonic#"($src1+#$offset)",
[]>;
@ -1006,7 +1006,7 @@ def LDd_GP : LDInst2<(outs DoubleRegs:$dst),
multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2++#$offset)",
@ -1017,7 +1017,7 @@ multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
Operand ImmOp, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
// Predicate new
let Predicates = [HasV4T], validSubTargets = HasV4SubT in
defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
@ -1029,8 +1029,8 @@ multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
let BaseOpcode = "POST_"#BaseOp in {
let isPredicable = 1 in
def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
(ins IntRegs:$src1, ImmOp:$offset),
def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
(ins IntRegs:$src1, ImmOp:$offset),
"$dst = "#mnemonic#"($src1++#$offset)",
[],
"$src1 = $dst2">;
@ -1441,7 +1441,7 @@ def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : STInst2<(outs),
def NAME : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($addr) = $src2",
@ -1450,7 +1450,7 @@ multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
@ -1465,7 +1465,7 @@ multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
def #NAME# : STInst2<(outs),
def NAME : STInst2<(outs),
(ins MEMri:$addr, RC:$src),
#mnemonic#"($addr) = $src",
[]>;
@ -1507,7 +1507,7 @@ def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : STInst2<(outs),
def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = $src4",
@ -1517,7 +1517,7 @@ multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
defm _c#NAME# : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
@ -1533,7 +1533,7 @@ multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
def #NAME# : STInst2<(outs),
def NAME : STInst2<(outs),
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
#mnemonic#"($src1+#$src2) = $src3",
[]>;

48
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -419,7 +419,7 @@ def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : LDInst2<(outs RC:$dst),
def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
@ -428,9 +428,9 @@ multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
}
}
@ -438,7 +438,7 @@ let neverHasSideEffects = 1 in
multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
def #NAME#_V4 : LDInst2<(outs RC:$dst),
def NAME#_V4 : LDInst2<(outs RC:$dst),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
"$dst = "#mnemonic#"($src1+$src2<<#$offset)",
[]>, Requires<[HasV4T]>;
@ -1519,7 +1519,7 @@ def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : STInst2<(outs),
def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@ -1530,9 +1530,9 @@ multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
}
}
@ -1540,7 +1540,7 @@ let isNVStorable = 1 in
multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
def #NAME#_V4 : STInst2<(outs),
def NAME#_V4 : STInst2<(outs),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
#mnemonic#"($src1+$src2<<#$src3) = $src4",
[]>,
@ -1558,7 +1558,7 @@ multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME#_nv_V4 : NVInst_V4<(outs),
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@ -1569,9 +1569,9 @@ multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
}
}
@ -1579,7 +1579,7 @@ let mayStore = 1, isNVStore = 1 in
multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
def #NAME#_nv_V4 : NVInst_V4<(outs),
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
#mnemonic#"($src1+$src2<<#$src3) = $src4.new",
[]>,
@ -1683,7 +1683,7 @@ def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME# : STInst2<(outs),
def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = #$src4",
@ -1693,9 +1693,9 @@ multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
}
}
@ -1703,7 +1703,7 @@ let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
def #NAME#_V4 : STInst2<(outs),
def NAME#_V4 : STInst2<(outs),
(ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
#mnemonic#"($src1+#$src2) = #$src3",
[]>,
@ -2357,7 +2357,7 @@ def : Pat<(store (i32 IntRegs:$src1),
multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
Operand predImmOp, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME#_nv_V4 : NVInst_V4<(outs),
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = $src4.new",
@ -2368,9 +2368,9 @@ multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
}
}
@ -2382,7 +2382,7 @@ multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
def #NAME#_nv_V4 : NVInst_V4<(outs),
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
#mnemonic#"($src1+#$src2) = $src3.new",
[]>,
@ -2410,7 +2410,7 @@ let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
def #NAME#_nv_V4 : NVInst_V4<(outs),
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($addr) = $src2.new",
@ -2420,10 +2420,10 @@ multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
defm _c#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
}
}
@ -2434,7 +2434,7 @@ multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
def #NAME#_nv_V4 : NVInst_V4<(outs),
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins MEMri:$addr, RC:$src),
#mnemonic#"($addr) = $src.new",
[]>,

16
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -37,19 +37,19 @@ def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
let DecoderNamespace = "Mips64" in {
multiclass Atomic2Ops64<PatFrag Op> {
def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
}
}
multiclass AtomicCmpSwap64<PatFrag Op> {
def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
}
}

38
lib/Target/Mips/MipsInstrInfo.td
View File

@ -420,8 +420,8 @@ class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
multiclass LoadM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
@ -429,8 +429,8 @@ multiclass LoadM<string opstr, RegisterClass RC,
multiclass StoreM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
@ -455,20 +455,20 @@ class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
}
multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
def #NAME# : LoadLeftRight<opstr, OpNode, RC, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
Requires<[IsN64, HasStdEnc]> {
def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
def #NAME# : StoreLeftRight<opstr, OpNode, RC, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
Requires<[IsN64, HasStdEnc]> {
def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
@ -678,9 +678,9 @@ class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
multiclass Atomic2Ops32<PatFrag Op> {
def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}
@ -691,10 +691,10 @@ class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
multiclass AtomicCmpSwap32<PatFrag Op> {
def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
Requires<[NotN64, HasStdEnc]>;
def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}