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https://github.com/RPCS3/llvm.git
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Hexagon V5 FP Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sirish Pande
parent
55ba5dff3c
commit
7517bbc91a
@ -28,6 +28,8 @@ def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
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"Hexagon v3">;
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def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
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"Hexagon v4">;
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def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
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"Hexagon v5">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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@ -52,6 +54,8 @@ class Proc<string Name, ProcessorItineraries Itin,
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def : Proc<"hexagonv2", HexagonItineraries, [ArchV2]>;
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def : Proc<"hexagonv3", HexagonItineraries, [ArchV2, ArchV3]>;
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def : Proc<"hexagonv4", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4]>;
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def : Proc<"hexagonv5", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
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// Hexagon Uses the MC printer for assembler output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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@ -17,8 +17,8 @@
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// Hexagon 32-bit C return-value convention.
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def RetCC_Hexagon32 : CallingConv<[
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
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CCIfType<[i64], CCAssignToReg<[D0, D1, D2]>>,
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CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
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CCIfType<[i64, f64], CCAssignToReg<[D0, D1, D2]>>,
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// Alternatively, they are assigned to the stack in 4-byte aligned units.
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CCAssignToStack<4, 4>
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@ -27,8 +27,8 @@ def RetCC_Hexagon32 : CallingConv<[
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// Hexagon 32-bit C Calling convention.
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def CC_Hexagon32 : CallingConv<[
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// All arguments get passed in integer registers if there is space.
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CCIfType<[i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
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CCIfType<[i64], CCAssignToReg<[D0, D1, D2]>>,
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CCIfType<[f32, i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
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CCIfType<[f64, i64], CCAssignToReg<[D0, D1, D2]>>,
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// Alternatively, they are assigned to the stack in 4-byte aligned units.
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CCAssignToStack<4, 4>
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@ -90,7 +90,9 @@ public:
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SDNode *SelectMul(SDNode *N);
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SDNode *SelectZeroExtend(SDNode *N);
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SDNode *SelectIntrinsicWOChain(SDNode *N);
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SDNode *SelectIntrinsicWChain(SDNode *N);
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SDNode *SelectConstant(SDNode *N);
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SDNode *SelectConstantFP(SDNode *N);
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SDNode *SelectAdd(SDNode *N);
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// Include the pieces autogenerated from the target description.
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@ -1158,6 +1160,25 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
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return SelectCode(N);
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}
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//
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// Map floating point constant values.
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//
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SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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APFloat APF = CN->getValueAPF();
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if (N->getValueType(0) == MVT::f32) {
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return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
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CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
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}
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else if (N->getValueType(0) == MVT::f64) {
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return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
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CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
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}
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return SelectCode(N);
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}
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//
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// Map predicate true (encoded as -1 in LLVM) to a XOR.
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@ -1234,6 +1255,9 @@ SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
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case ISD::Constant:
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return SelectConstant(N);
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case ISD::ConstantFP:
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return SelectConstantFP(N);
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case ISD::ADD:
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return SelectAdd(N);
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@ -103,12 +103,12 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::i32) {
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if (LocVT == MVT::i32 || LocVT == MVT::f32) {
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ofst = State.AllocateStack(4, 4);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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return false;
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}
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if (LocVT == MVT::i64) {
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if (LocVT == MVT::i64 || LocVT == MVT::f64) {
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ofst = State.AllocateStack(8, 8);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
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return false;
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@ -142,12 +142,12 @@ CC_Hexagon (unsigned ValNo, MVT ValVT,
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LocInfo = CCValAssign::AExt;
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}
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if (LocVT == MVT::i32) {
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if (LocVT == MVT::i32 || LocVT == MVT::f32) {
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if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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return false;
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}
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if (LocVT == MVT::i64) {
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if (LocVT == MVT::i64 || LocVT == MVT::f64) {
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if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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return false;
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}
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@ -217,12 +217,12 @@ static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
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LocInfo = CCValAssign::AExt;
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}
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if (LocVT == MVT::i32) {
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if (LocVT == MVT::i32 || LocVT == MVT::f32) {
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if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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return false;
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}
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if (LocVT == MVT::i64) {
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if (LocVT == MVT::i64 || LocVT == MVT::f64) {
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if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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return false;
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}
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@ -234,7 +234,7 @@ static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
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MVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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if (LocVT == MVT::i32) {
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if (LocVT == MVT::i32 || LocVT == MVT::f32) {
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if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return false;
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@ -249,7 +249,7 @@ static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
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static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
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MVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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if (LocVT == MVT::i64) {
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if (LocVT == MVT::i64 || LocVT == MVT::f64) {
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if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return false;
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@ -839,7 +839,8 @@ const {
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// 1. int, long long, ptr args that get allocated in register.
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// 2. Large struct that gets an register to put its address in.
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EVT RegVT = VA.getLocVT();
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if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
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if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
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RegVT == MVT::i32 || RegVT == MVT::f32) {
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unsigned VReg =
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RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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@ -918,14 +919,33 @@ HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue CC = Op.getOperand(4);
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SDValue TrueVal = Op.getOperand(2);
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SDValue FalseVal = Op.getOperand(3);
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DebugLoc dl = Op.getDebugLoc();
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SDNode* OpNode = Op.getNode();
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EVT SVT = OpNode->getValueType(0);
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SDValue Cond = DAG.getNode(ISD::SETCC, Op.getDebugLoc(), MVT::i1,
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Op.getOperand(2), Op.getOperand(3),
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Op.getOperand(4));
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return DAG.getNode(ISD::SELECT, Op.getDebugLoc(), OpNode->getValueType(0),
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Cond, Op.getOperand(0),
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Op.getOperand(1));
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SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
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return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal);
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}
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SDValue
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HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
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EVT ValTy = Op.getValueType();
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DebugLoc dl = Op.getDebugLoc();
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ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
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SDValue Res;
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if (CP->isMachineConstantPoolEntry())
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Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
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CP->getAlignment());
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else
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Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
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CP->getAlignment());
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return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res);
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}
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SDValue
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@ -1010,10 +1030,17 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
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: TargetLowering(targetmachine, new HexagonTargetObjectFile()),
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TM(targetmachine) {
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const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
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// Set up the register classes.
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addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
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addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
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if (QRI->Subtarget.hasV5TOps()) {
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addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
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addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
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}
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addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
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computeRegisterProperties();
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@ -1028,32 +1055,16 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
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//
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// Library calls for unsupported operations
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//
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setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
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setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
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setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
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setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
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setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
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setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
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setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
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setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
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setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
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setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
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setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
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setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
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setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
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setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
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setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
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setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
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setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
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setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
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setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
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setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
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setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
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@ -1082,93 +1093,185 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
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setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
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setOperationAction(ISD::FDIV, MVT::f64, Expand);
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setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
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setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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setOperationAction(ISD::FSIN, MVT::f64, Expand);
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setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
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if (QRI->Subtarget.hasV5TOps()) {
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// Hexagon V5 Support.
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setOperationAction(ISD::FADD, MVT::f32, Legal);
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setOperationAction(ISD::FADD, MVT::f64, Legal);
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setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
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setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal);
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setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal);
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setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
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setOperationAction(ISD::FADD, MVT::f64, Expand);
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setCondCodeAction(ISD::SETOGE, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOGE, MVT::f64, Legal);
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setCondCodeAction(ISD::SETUGE, MVT::f32, Legal);
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setCondCodeAction(ISD::SETUGE, MVT::f64, Legal);
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setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
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setOperationAction(ISD::FADD, MVT::f32, Expand);
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setCondCodeAction(ISD::SETOGT, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOGT, MVT::f64, Legal);
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setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
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setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
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setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
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setOperationAction(ISD::FADD, MVT::f32, Expand);
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setCondCodeAction(ISD::SETOLE, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOLE, MVT::f64, Legal);
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setCondCodeAction(ISD::SETOLT, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOLT, MVT::f64, Legal);
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setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
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setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
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setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
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setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
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setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
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setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
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setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
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setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
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setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
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setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
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setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
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setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
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setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
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setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
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setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
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setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
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setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
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setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
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setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
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setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
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setOperationAction(ISD::FABS, MVT::f32, Legal);
|
||||
setOperationAction(ISD::FABS, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
|
||||
setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FNEG, MVT::f32, Legal);
|
||||
setOperationAction(ISD::FNEG, MVT::f64, Expand);
|
||||
} else {
|
||||
|
||||
setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
|
||||
setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
|
||||
// Expand fp<->uint.
|
||||
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
|
||||
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
|
||||
setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
|
||||
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
|
||||
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
|
||||
setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
|
||||
setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
|
||||
setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
|
||||
|
||||
setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
|
||||
setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
|
||||
|
||||
setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
|
||||
setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
|
||||
|
||||
setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
|
||||
setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
|
||||
|
||||
setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
|
||||
setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
|
||||
|
||||
setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
|
||||
setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
|
||||
|
||||
setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
|
||||
setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
|
||||
|
||||
setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
|
||||
setOperationAction(ISD::FADD, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
|
||||
setOperationAction(ISD::FADD, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
|
||||
setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
|
||||
setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
|
||||
setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
|
||||
setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
|
||||
setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
|
||||
setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
|
||||
setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
|
||||
setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
|
||||
setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
|
||||
setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
|
||||
setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
|
||||
setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
|
||||
setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
|
||||
setOperationAction(ISD::FMUL, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
|
||||
setOperationAction(ISD::MUL, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
|
||||
setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
|
||||
|
||||
setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
|
||||
setOperationAction(ISD::SUB, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
|
||||
setOperationAction(ISD::SUB, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
|
||||
setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
|
||||
setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
|
||||
setCondCodeAction(ISD::SETO, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
|
||||
setCondCodeAction(ISD::SETO, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
|
||||
setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
|
||||
|
||||
setOperationAction(ISD::FABS, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FABS, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FNEG, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FNEG, MVT::f64, Expand);
|
||||
}
|
||||
|
||||
setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
|
||||
setOperationAction(ISD::SREM, MVT::i32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
|
||||
setOperationAction(ISD::FMUL, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
|
||||
setOperationAction(ISD::MUL, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
|
||||
setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
|
||||
|
||||
|
||||
setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
|
||||
setOperationAction(ISD::SUB, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
|
||||
setOperationAction(ISD::SUB, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
|
||||
setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
|
||||
setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
|
||||
setCondCodeAction(ISD::SETO, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
|
||||
setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
|
||||
|
||||
setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
|
||||
setCondCodeAction(ISD::SETO, MVT::f32, Expand);
|
||||
|
||||
setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
|
||||
setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
|
||||
|
||||
setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
|
||||
setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
|
||||
setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
|
||||
@ -1208,20 +1311,33 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
|
||||
|
||||
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
|
||||
|
||||
// Expand fp<->uint.
|
||||
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
|
||||
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
|
||||
|
||||
// Hexagon has no select or setcc: expand to SELECT_CC.
|
||||
setOperationAction(ISD::SELECT, MVT::f32, Expand);
|
||||
setOperationAction(ISD::SELECT, MVT::f64, Expand);
|
||||
|
||||
// Lower SELECT_CC to SETCC and SELECT.
|
||||
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
|
||||
setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
|
||||
// This is a workaround documented in DAGCombiner.cpp:2892 We don't
|
||||
// support SELECT_CC on every type.
|
||||
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
|
||||
|
||||
if (QRI->Subtarget.hasV5TOps()) {
|
||||
|
||||
// We need to make the operation type of SELECT node to be Custom,
|
||||
// such that we don't go into the infinite loop of
|
||||
// select -> setcc -> select_cc -> select loop.
|
||||
setOperationAction(ISD::SELECT, MVT::f32, Custom);
|
||||
setOperationAction(ISD::SELECT, MVT::f64, Custom);
|
||||
|
||||
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
|
||||
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
|
||||
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
|
||||
|
||||
} else {
|
||||
|
||||
// Hexagon has no select or setcc: expand to SELECT_CC.
|
||||
setOperationAction(ISD::SELECT, MVT::f32, Expand);
|
||||
setOperationAction(ISD::SELECT, MVT::f64, Expand);
|
||||
|
||||
// This is a workaround documented in DAGCombiner.cpp:2892 We don't
|
||||
// support SELECT_CC on every type.
|
||||
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
|
||||
|
||||
}
|
||||
|
||||
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
|
||||
setOperationAction(ISD::BRIND, MVT::Other, Expand);
|
||||
@ -1307,22 +1423,22 @@ const char*
|
||||
HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
switch (Opcode) {
|
||||
default: return 0;
|
||||
case HexagonISD::CONST32: return "HexagonISD::CONST32";
|
||||
case HexagonISD::CONST32: return "HexagonISD::CONST32";
|
||||
case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
|
||||
case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
|
||||
case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
|
||||
case HexagonISD::BRICC: return "HexagonISD::BRICC";
|
||||
case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
|
||||
case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
|
||||
case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
|
||||
case HexagonISD::Hi: return "HexagonISD::Hi";
|
||||
case HexagonISD::Lo: return "HexagonISD::Lo";
|
||||
case HexagonISD::FTOI: return "HexagonISD::FTOI";
|
||||
case HexagonISD::ITOF: return "HexagonISD::ITOF";
|
||||
case HexagonISD::CALL: return "HexagonISD::CALL";
|
||||
case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
|
||||
case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
|
||||
case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
|
||||
case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
|
||||
case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
|
||||
case HexagonISD::BRICC: return "HexagonISD::BRICC";
|
||||
case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
|
||||
case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
|
||||
case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
|
||||
case HexagonISD::Hi: return "HexagonISD::Hi";
|
||||
case HexagonISD::Lo: return "HexagonISD::Lo";
|
||||
case HexagonISD::FTOI: return "HexagonISD::FTOI";
|
||||
case HexagonISD::ITOF: return "HexagonISD::ITOF";
|
||||
case HexagonISD::CALL: return "HexagonISD::CALL";
|
||||
case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
|
||||
case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
|
||||
case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
|
||||
}
|
||||
}
|
||||
|
||||
@ -1347,9 +1463,10 @@ SDValue
|
||||
HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
switch (Op.getOpcode()) {
|
||||
default: llvm_unreachable("Should not custom lower this!");
|
||||
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
||||
// Frame & Return address. Currently unimplemented.
|
||||
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
|
||||
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
|
||||
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
|
||||
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
|
||||
case ISD::GlobalTLSAddress:
|
||||
llvm_unreachable("TLS not implemented for Hexagon.");
|
||||
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
|
||||
@ -1359,9 +1476,10 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::BR_JT: return LowerBR_JT(Op, DAG);
|
||||
|
||||
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
|
||||
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
|
||||
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
|
||||
case ISD::SELECT: return Op;
|
||||
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
|
||||
case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
|
||||
case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
|
||||
|
||||
}
|
||||
}
|
||||
@ -1404,8 +1522,10 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
|
||||
case MVT::i32:
|
||||
case MVT::i16:
|
||||
case MVT::i8:
|
||||
case MVT::f32:
|
||||
return std::make_pair(0U, &Hexagon::IntRegsRegClass);
|
||||
case MVT::i64:
|
||||
case MVT::f64:
|
||||
return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
|
||||
}
|
||||
default:
|
||||
@ -1416,6 +1536,14 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
|
||||
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
||||
}
|
||||
|
||||
/// isFPImmLegal - Returns true if the target can instruction select the
|
||||
/// specified FP immediate natively. If false, the legalizer will
|
||||
/// materialize the FP immediate as a load from a constant pool.
|
||||
bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
|
||||
const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
|
||||
return QRI->Subtarget.hasV5TOps();
|
||||
}
|
||||
|
||||
/// isLegalAddressingMode - Return true if the addressing mode represented by
|
||||
/// AM is legal for this target, for a load/store of the specified type.
|
||||
bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
|
||||
|
||||
@ -27,6 +27,7 @@ namespace llvm {
|
||||
|
||||
CONST32,
|
||||
CONST32_GP, // For marking data present in GP.
|
||||
FCONST32,
|
||||
SETCC,
|
||||
ADJDYNALLOC,
|
||||
ARGEXTEND,
|
||||
@ -48,6 +49,7 @@ namespace llvm {
|
||||
BR_JT, // Jump table.
|
||||
BARRIER, // Memory barrier.
|
||||
WrapperJT,
|
||||
WrapperCP,
|
||||
TC_RETURN
|
||||
};
|
||||
}
|
||||
@ -128,6 +130,7 @@ namespace llvm {
|
||||
MachineBasicBlock *BB) const;
|
||||
|
||||
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
||||
virtual EVT getSetCCResultType(EVT VT) const {
|
||||
return MVT::i1;
|
||||
}
|
||||
@ -150,6 +153,7 @@ namespace llvm {
|
||||
/// mode is legal for a load/store of any legal type.
|
||||
/// TODO: Handle pre/postinc as well.
|
||||
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
|
||||
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
||||
|
||||
/// isLegalICmpImmediate - Return true if the specified immediate is legal
|
||||
/// icmp immediate, that is the target has icmp instructions which can
|
||||
|
||||
@ -180,7 +180,7 @@ class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
// Definition of the instruction class NOT CHANGED.
|
||||
// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
|
||||
class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
string cstr>
|
||||
string cstr>
|
||||
: InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
|
||||
bits<5> rd;
|
||||
bits<5> rs;
|
||||
@ -203,7 +203,7 @@ class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
// Definition of the instruction class NOT CHANGED.
|
||||
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
|
||||
class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
string cstr>
|
||||
string cstr>
|
||||
: InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
|
||||
// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
|
||||
// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
|
||||
|
||||
@ -444,14 +444,15 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
|
||||
|
||||
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
||||
const TargetRegisterClass *TRC;
|
||||
if (VT == MVT::i1)
|
||||
if (VT == MVT::i1) {
|
||||
TRC = &Hexagon::PredRegsRegClass;
|
||||
else if (VT == MVT::i32)
|
||||
} else if (VT == MVT::i32 || VT == MVT::f32) {
|
||||
TRC = &Hexagon::IntRegsRegClass;
|
||||
else if (VT == MVT::i64)
|
||||
} else if (VT == MVT::i64 || VT == MVT::f64) {
|
||||
TRC = &Hexagon::DoubleRegsRegClass;
|
||||
else
|
||||
} else {
|
||||
llvm_unreachable("Cannot handle this register class");
|
||||
}
|
||||
|
||||
unsigned NewReg = RegInfo.createVirtualRegister(TRC);
|
||||
return NewReg;
|
||||
@ -714,8 +715,13 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
|
||||
|
||||
// TFR_FI
|
||||
case Hexagon::TFR_FI_immext_V4:
|
||||
return true;
|
||||
|
||||
// TFRI_F
|
||||
case Hexagon::TFRI_f:
|
||||
case Hexagon::TFRI_cPt_f:
|
||||
case Hexagon::TFRI_cNotPt_f:
|
||||
case Hexagon::CONST64_Float_Real:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1892,6 +1898,9 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
|
||||
case Hexagon::TFR:
|
||||
return !invertPredicate ? Hexagon::TFR_cPt :
|
||||
Hexagon::TFR_cNotPt;
|
||||
case Hexagon::TFRI_f:
|
||||
return !invertPredicate ? Hexagon::TFRI_cPt_f :
|
||||
Hexagon::TFRI_cNotPt_f;
|
||||
case Hexagon::TFRI:
|
||||
return !invertPredicate ? Hexagon::TFRI_cPt :
|
||||
Hexagon::TFRI_cNotPt;
|
||||
@ -2330,13 +2339,17 @@ isValidOffset(const int Opcode, const int Offset) const {
|
||||
switch(Opcode) {
|
||||
|
||||
case Hexagon::LDriw:
|
||||
case Hexagon::LDriw_f:
|
||||
case Hexagon::STriw:
|
||||
case Hexagon::STriw_f:
|
||||
assert((Offset % 4 == 0) && "Offset has incorrect alignment");
|
||||
return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
|
||||
(Offset <= Hexagon_MEMW_OFFSET_MAX);
|
||||
|
||||
case Hexagon::LDrid:
|
||||
case Hexagon::LDrid_f:
|
||||
case Hexagon::STrid:
|
||||
case Hexagon::STrid_f:
|
||||
assert((Offset % 8 == 0) && "Offset has incorrect alignment");
|
||||
return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
|
||||
(Offset <= Hexagon_MEMD_OFFSET_MAX);
|
||||
|
||||
@ -25,7 +25,10 @@ def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
|
||||
def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
|
||||
def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
|
||||
def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
|
||||
def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
|
||||
def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
|
||||
def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
|
||||
def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
|
||||
|
||||
// Addressing modes.
|
||||
def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
|
||||
@ -242,7 +245,6 @@ def TFR64 : ALU32_ri<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
|
||||
"$dst = $src1",
|
||||
[]>;
|
||||
|
||||
|
||||
// Transfer control register.
|
||||
let neverHasSideEffects = 1 in
|
||||
def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
|
||||
@ -1861,7 +1863,7 @@ def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
|
||||
"$src3 = $dst">;
|
||||
|
||||
// if (!Pv) memd(Rx++#s4:3)=Rtt
|
||||
let AddedComplexity = 10, neverHasSideEffects = 1,
|
||||
let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
|
||||
@ -2169,28 +2171,49 @@ def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/BIT +
|
||||
//===----------------------------------------------------------------------===//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/BIT -
|
||||
//===----------------------------------------------------------------------===//
|
||||
// clrbit.
|
||||
def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
"$dst = clrbit($src1, #$src2)",
|
||||
[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
|
||||
(not
|
||||
(shl 1, u5ImmPred:$src2))))]>;
|
||||
|
||||
def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
"$dst = clrbit($src1, #$src2)",
|
||||
[]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/COMPLEX +
|
||||
//===----------------------------------------------------------------------===//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/COMPLEX -
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
|
||||
def : Pat <(and (i32 IntRegs:$src1), 2147483647),
|
||||
(CLRBIT_31 (i32 IntRegs:$src1), 31)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/PERM +
|
||||
//===----------------------------------------------------------------------===//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/PERM -
|
||||
//===----------------------------------------------------------------------===//
|
||||
// setbit.
|
||||
def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
"$dst = setbit($src1, #$src2)",
|
||||
[(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
|
||||
(shl 1, u5ImmPred:$src2)))]>;
|
||||
|
||||
// Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
|
||||
def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
"$dst = setbit($src1, #$src2)",
|
||||
[]>;
|
||||
|
||||
def : Pat <(or (i32 IntRegs:$src1), -2147483648),
|
||||
(SETBIT_31 (i32 IntRegs:$src1), 31)>;
|
||||
|
||||
// togglebit.
|
||||
def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
"$dst = setbit($src1, #$src2)",
|
||||
[(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
|
||||
(shl 1, u5ImmPred:$src2)))]>;
|
||||
|
||||
// Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
|
||||
def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
|
||||
"$dst = togglebit($src1, #$src2)",
|
||||
[]>;
|
||||
|
||||
def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
|
||||
(TOGBIT_31 (i32 IntRegs:$src1), 31)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/PRED +
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Predicate transfer.
|
||||
let neverHasSideEffects = 1 in
|
||||
def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
|
||||
@ -3519,3 +3542,14 @@ include "HexagonInstrInfoV4.td"
|
||||
// V4 Instructions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V5 Instructions +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonInstrInfoV5.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V5 Instructions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
|
||||
@ -63,6 +63,7 @@ const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
|
||||
return CalleeSavedRegsV2;
|
||||
case HexagonSubtarget::V3:
|
||||
case HexagonSubtarget::V4:
|
||||
case HexagonSubtarget::V5:
|
||||
return CalleeSavedRegsV3;
|
||||
}
|
||||
llvm_unreachable("Callee saved registers requested for unknown architecture "
|
||||
@ -109,6 +110,7 @@ HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
|
||||
return CalleeSavedRegClassesV2;
|
||||
case HexagonSubtarget::V3:
|
||||
case HexagonSubtarget::V4:
|
||||
case HexagonSubtarget::V5:
|
||||
return CalleeSavedRegClassesV3;
|
||||
}
|
||||
llvm_unreachable("Callee saved register classes requested for unknown "
|
||||
@ -179,11 +181,13 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
// r0 = add(r30, #10000)
|
||||
// r0 = memw(r0)
|
||||
if ( (MI.getOpcode() == Hexagon::LDriw) ||
|
||||
(MI.getOpcode() == Hexagon::LDrid) ||
|
||||
(MI.getOpcode() == Hexagon::LDrih) ||
|
||||
(MI.getOpcode() == Hexagon::LDriuh) ||
|
||||
(MI.getOpcode() == Hexagon::LDrib) ||
|
||||
(MI.getOpcode() == Hexagon::LDriub) ) {
|
||||
(MI.getOpcode() == Hexagon::LDrid) ||
|
||||
(MI.getOpcode() == Hexagon::LDrih) ||
|
||||
(MI.getOpcode() == Hexagon::LDriuh) ||
|
||||
(MI.getOpcode() == Hexagon::LDrib) ||
|
||||
(MI.getOpcode() == Hexagon::LDriub) ||
|
||||
(MI.getOpcode() == Hexagon::LDriw_f) ||
|
||||
(MI.getOpcode() == Hexagon::LDrid_f)) {
|
||||
unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
|
||||
*getSubRegisters(MI.getOperand(0).getReg()) :
|
||||
MI.getOperand(0).getReg();
|
||||
@ -203,10 +207,13 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
|
||||
MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
|
||||
MI.getOperand(i+1).ChangeToImmediate(0);
|
||||
} else if ((MI.getOpcode() == Hexagon::STriw) ||
|
||||
} else if ((MI.getOpcode() == Hexagon::STriw_indexed) ||
|
||||
(MI.getOpcode() == Hexagon::STriw) ||
|
||||
(MI.getOpcode() == Hexagon::STrid) ||
|
||||
(MI.getOpcode() == Hexagon::STrih) ||
|
||||
(MI.getOpcode() == Hexagon::STrib)) {
|
||||
(MI.getOpcode() == Hexagon::STrib) ||
|
||||
(MI.getOpcode() == Hexagon::STrid_f) ||
|
||||
(MI.getOpcode() == Hexagon::STriw_f)) {
|
||||
// For stores, we need a reserved register. Change
|
||||
// memw(r30 + #10000) = r0 to:
|
||||
//
|
||||
|
||||
@ -131,6 +131,9 @@ let Namespace = "Hexagon" in {
|
||||
def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>;
|
||||
def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>;
|
||||
|
||||
def M0 : Rc<6, "m0">, DwarfRegNum<[71]>;
|
||||
def M1 : Rc<7, "m1">, DwarfRegNum<[72]>;
|
||||
|
||||
def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct?
|
||||
def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct?
|
||||
}
|
||||
@ -140,15 +143,13 @@ let Namespace = "Hexagon" in {
|
||||
// FIXME: the register order should be defined in terms of the preferred
|
||||
// allocation order...
|
||||
//
|
||||
def IntRegs : RegisterClass<"Hexagon", [i32], 32,
|
||||
def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,
|
||||
(add (sequence "R%u", 0, 9),
|
||||
(sequence "R%u", 12, 28),
|
||||
R10, R11, R29, R30, R31)> {
|
||||
}
|
||||
|
||||
|
||||
|
||||
def DoubleRegs : RegisterClass<"Hexagon", [i64], 64,
|
||||
def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64,
|
||||
(add (sequence "D%u", 0, 4),
|
||||
(sequence "D%u", 6, 13), D5, D14, D15)>;
|
||||
|
||||
@ -160,6 +161,7 @@ def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))>
|
||||
|
||||
def CRRegs : RegisterClass<"Hexagon", [i32], 32,
|
||||
(add (sequence "LC%u", 0, 1),
|
||||
(sequence "SA%u", 0, 1), PC, GP)> {
|
||||
(sequence "SA%u", 0, 1),
|
||||
(sequence "M%u", 0, 1), PC, GP)> {
|
||||
let Size = 32;
|
||||
}
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
// {p0 = cmp.eq(r0,r1)}
|
||||
// {r3 = mux(p0,#1,#3)}
|
||||
//
|
||||
// This requires two packets. If we use .new predicated immediate transfers,
|
||||
// This requires two packets. If we use .new predicated immediate transfers,
|
||||
// then we can do this in a single packet, e.g.:
|
||||
//
|
||||
// {p0 = cmp.eq(r0,r1)
|
||||
@ -81,40 +81,126 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
|
||||
for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
|
||||
++MII) {
|
||||
MachineInstr *MI = MII;
|
||||
int Opc = MI->getOpcode();
|
||||
if (Opc == Hexagon::TFR_condset_rr) {
|
||||
int Opc1, Opc2;
|
||||
switch(MI->getOpcode()) {
|
||||
case Hexagon::TFR_condset_rr:
|
||||
case Hexagon::TFR_condset_rr_f:
|
||||
case Hexagon::TFR_condset_rr64_f: {
|
||||
int DestReg = MI->getOperand(0).getReg();
|
||||
int SrcReg1 = MI->getOperand(2).getReg();
|
||||
int SrcReg2 = MI->getOperand(3).getReg();
|
||||
|
||||
int DestReg = MI->getOperand(0).getReg();
|
||||
int SrcReg1 = MI->getOperand(2).getReg();
|
||||
int SrcReg2 = MI->getOperand(3).getReg();
|
||||
if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
|
||||
MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
|
||||
Opc1 = Hexagon::TFR_cPt;
|
||||
Opc2 = Hexagon::TFR_cNotPt;
|
||||
}
|
||||
else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
|
||||
Opc1 = Hexagon::TFR64_cPt;
|
||||
Opc2 = Hexagon::TFR64_cNotPt;
|
||||
}
|
||||
|
||||
// Minor optimization: do not emit the predicated copy if the source and
|
||||
// the destination is the same register
|
||||
if (DestReg != SrcReg1) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cPt),
|
||||
DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
|
||||
// Minor optimization: do not emit the predicated copy if the source
|
||||
// and the destination is the same register.
|
||||
if (DestReg != SrcReg1) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
|
||||
DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
|
||||
}
|
||||
if (DestReg != SrcReg2) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
|
||||
DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
|
||||
}
|
||||
MII = MBB->erase(MI);
|
||||
--MII;
|
||||
break;
|
||||
}
|
||||
if (DestReg != SrcReg2) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cNotPt),
|
||||
DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
|
||||
case Hexagon::TFR_condset_ri:
|
||||
case Hexagon::TFR_condset_ri_f: {
|
||||
int DestReg = MI->getOperand(0).getReg();
|
||||
int SrcReg1 = MI->getOperand(2).getReg();
|
||||
|
||||
// Do not emit the predicated copy if the source and the destination
|
||||
// is the same register.
|
||||
if (DestReg != SrcReg1) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFR_cPt), DestReg).
|
||||
addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
|
||||
}
|
||||
if (MI->getOpcode() == Hexagon::TFR_condset_ri ) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cNotPt), DestReg).
|
||||
addReg(MI->getOperand(1).getReg()).
|
||||
addImm(MI->getOperand(3).getImm());
|
||||
} else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
|
||||
addReg(MI->getOperand(1).getReg()).
|
||||
addFPImm(MI->getOperand(3).getFPImm());
|
||||
}
|
||||
|
||||
MII = MBB->erase(MI);
|
||||
--MII;
|
||||
break;
|
||||
}
|
||||
case Hexagon::TFR_condset_ir:
|
||||
case Hexagon::TFR_condset_ir_f: {
|
||||
int DestReg = MI->getOperand(0).getReg();
|
||||
int SrcReg2 = MI->getOperand(3).getReg();
|
||||
|
||||
if (MI->getOpcode() == Hexagon::TFR_condset_ir ) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cPt), DestReg).
|
||||
addReg(MI->getOperand(1).getReg()).
|
||||
addImm(MI->getOperand(2).getImm());
|
||||
} else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cPt_f), DestReg).
|
||||
addReg(MI->getOperand(1).getReg()).
|
||||
addFPImm(MI->getOperand(2).getFPImm());
|
||||
}
|
||||
|
||||
// Do not emit the predicated copy if the source and
|
||||
// the destination is the same register.
|
||||
if (DestReg != SrcReg2) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFR_cNotPt), DestReg).
|
||||
addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
|
||||
}
|
||||
MII = MBB->erase(MI);
|
||||
--MII;
|
||||
break;
|
||||
}
|
||||
case Hexagon::TFR_condset_ii:
|
||||
case Hexagon::TFR_condset_ii_f: {
|
||||
int DestReg = MI->getOperand(0).getReg();
|
||||
int SrcReg1 = MI->getOperand(1).getReg();
|
||||
|
||||
if (MI->getOpcode() == Hexagon::TFR_condset_ii ) {
|
||||
int Immed1 = MI->getOperand(2).getImm();
|
||||
int Immed2 = MI->getOperand(3).getImm();
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cPt),
|
||||
DestReg).addReg(SrcReg1).addImm(Immed1);
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cNotPt),
|
||||
DestReg).addReg(SrcReg1).addImm(Immed2);
|
||||
} else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f ) {
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cPt_f), DestReg).
|
||||
addReg(SrcReg1).
|
||||
addFPImm(MI->getOperand(2).getFPImm());
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(),
|
||||
TII->get(Hexagon::TFRI_cNotPt_f), DestReg).
|
||||
addReg(SrcReg1).
|
||||
addFPImm(MI->getOperand(3).getFPImm());
|
||||
}
|
||||
MII = MBB->erase(MI);
|
||||
--MII;
|
||||
break;
|
||||
}
|
||||
MII = MBB->erase(MI);
|
||||
--MII;
|
||||
} else if (Opc == Hexagon::TFR_condset_ii) {
|
||||
int DestReg = MI->getOperand(0).getReg();
|
||||
int SrcReg1 = MI->getOperand(1).getReg();
|
||||
int Immed1 = MI->getOperand(2).getImm();
|
||||
int Immed2 = MI->getOperand(3).getImm();
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cPt),
|
||||
DestReg).addReg(SrcReg1).addImm(Immed1);
|
||||
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cNotPt),
|
||||
DestReg).addReg(SrcReg1).addImm(Immed2);
|
||||
MII = MBB->erase(MI);
|
||||
--MII;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
#include "HexagonSubtarget.h"
|
||||
#include "Hexagon.h"
|
||||
#include "HexagonRegisterInfo.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
using namespace llvm;
|
||||
@ -29,7 +30,13 @@ static cl::opt<bool>
|
||||
EnableMemOps(
|
||||
"enable-hexagon-memops",
|
||||
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed,
|
||||
cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
|
||||
cl::desc("Generate V4 memop instructions."));
|
||||
|
||||
static cl::opt<bool>
|
||||
EnableIEEERndNear(
|
||||
"enable-hexagon-ieee-rnd-near",
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(false),
|
||||
cl::desc("Generate non-chopped conversion from fp to int."));
|
||||
|
||||
HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
|
||||
HexagonGenSubtargetInfo(TT, CPU, FS),
|
||||
@ -45,6 +52,8 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
|
||||
break;
|
||||
case HexagonSubtarget::V4:
|
||||
break;
|
||||
case HexagonSubtarget::V5:
|
||||
break;
|
||||
default:
|
||||
llvm_unreachable("Unknown Architecture Version.");
|
||||
}
|
||||
@ -59,4 +68,10 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
|
||||
UseMemOps = true;
|
||||
else
|
||||
UseMemOps = false;
|
||||
|
||||
if (EnableIEEERndNear)
|
||||
ModeIEEERndNear = true;
|
||||
else
|
||||
ModeIEEERndNear = false;
|
||||
}
|
||||
|
||||
|
||||
@ -22,16 +22,18 @@
|
||||
#include "HexagonGenSubtargetInfo.inc"
|
||||
|
||||
#define Hexagon_SMALL_DATA_THRESHOLD 8
|
||||
#define Hexagon_SLOTS 4
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class HexagonSubtarget : public HexagonGenSubtargetInfo {
|
||||
|
||||
bool UseMemOps;
|
||||
bool ModeIEEERndNear;
|
||||
|
||||
public:
|
||||
enum HexagonArchEnum {
|
||||
V1, V2, V3, V4
|
||||
V1, V2, V3, V4, V5
|
||||
};
|
||||
|
||||
HexagonArchEnum HexagonArchVersion;
|
||||
@ -55,7 +57,11 @@ public:
|
||||
bool hasV3TOps () const { return HexagonArchVersion >= V3; }
|
||||
bool hasV3TOpsOnly () const { return HexagonArchVersion == V3; }
|
||||
bool hasV4TOps () const { return HexagonArchVersion >= V4; }
|
||||
bool hasV4TOpsOnly () const { return HexagonArchVersion == V4; }
|
||||
bool useMemOps () const { return HexagonArchVersion >= V4 && UseMemOps; }
|
||||
bool hasV5TOps () const { return HexagonArchVersion >= V5; }
|
||||
bool hasV5TOpsOnly () const { return HexagonArchVersion == V5; }
|
||||
bool modeIEEERndNear () const { return ModeIEEERndNear; }
|
||||
|
||||
bool isSubtargetV2() const { return HexagonArchVersion == V2;}
|
||||
const std::string &getCPUString () const { return CPUString; }
|
||||
|
||||
@ -55,7 +55,9 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
|
||||
CodeModel::Model CM,
|
||||
CodeGenOpt::Level OL)
|
||||
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
|
||||
DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
|
||||
DataLayout("e-p:32:32:32-"
|
||||
"i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
|
||||
"f64:64:64-f32:32:32-a0:0-n32") ,
|
||||
Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
|
||||
TSInfo(*this),
|
||||
FrameLowering(Subtarget),
|
||||
|
||||
26
test/CodeGen/Hexagon/convertdptoint.ll
Normal file
26
test/CodeGen/Hexagon/convertdptoint.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate conversion from double precision floating point
|
||||
; to 32-bit int value in IEEE complaint mode in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}}):chop
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%i = alloca i32, align 4
|
||||
%a = alloca double, align 8
|
||||
%b = alloca double, align 8
|
||||
%c = alloca double, align 8
|
||||
store i32 0, i32* %retval
|
||||
store double 1.540000e+01, double* %a, align 8
|
||||
store double 9.100000e+00, double* %b, align 8
|
||||
%0 = load double* %a, align 8
|
||||
%1 = load double* %b, align 8
|
||||
%add = fadd double %0, %1
|
||||
store double %add, double* %c, align 8
|
||||
%2 = load double* %c, align 8
|
||||
%conv = fptosi double %2 to i32
|
||||
store i32 %conv, i32* %i, align 4
|
||||
%3 = load i32* %i, align 4
|
||||
ret i32 %3
|
||||
}
|
||||
27
test/CodeGen/Hexagon/convertdptoll.ll
Normal file
27
test/CodeGen/Hexagon/convertdptoll.ll
Normal file
@ -0,0 +1,27 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate conversion from double precision floating point
|
||||
; to 64-bit integer value in IEEE complaint mode in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = convert_df2d(r{{[0-9]+}}:{{[0-9]+}}):chop
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%i = alloca i64, align 8
|
||||
%a = alloca double, align 8
|
||||
%b = alloca double, align 8
|
||||
%c = alloca double, align 8
|
||||
store i32 0, i32* %retval
|
||||
store double 1.540000e+01, double* %a, align 8
|
||||
store double 9.100000e+00, double* %b, align 8
|
||||
%0 = load double* %a, align 8
|
||||
%1 = load double* %b, align 8
|
||||
%add = fadd double %0, %1
|
||||
store double %add, double* %c, align 8
|
||||
%2 = load double* %c, align 8
|
||||
%conv = fptosi double %2 to i64
|
||||
store i64 %conv, i64* %i, align 8
|
||||
%3 = load i64* %i, align 8
|
||||
%conv1 = trunc i64 %3 to i32
|
||||
ret i32 %conv1
|
||||
}
|
||||
26
test/CodeGen/Hexagon/convertsptoint.ll
Normal file
26
test/CodeGen/Hexagon/convertsptoint.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate conversion from single precision floating point
|
||||
; to 32-bit int value in IEEE complaint mode in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = convert_sf2w(r{{[0-9]+}}):chop
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%i = alloca i32, align 4
|
||||
%a = alloca float, align 4
|
||||
%b = alloca float, align 4
|
||||
%c = alloca float, align 4
|
||||
store i32 0, i32* %retval
|
||||
store float 0x402ECCCCC0000000, float* %a, align 4
|
||||
store float 0x4022333340000000, float* %b, align 4
|
||||
%0 = load float* %a, align 4
|
||||
%1 = load float* %b, align 4
|
||||
%add = fadd float %0, %1
|
||||
store float %add, float* %c, align 4
|
||||
%2 = load float* %c, align 4
|
||||
%conv = fptosi float %2 to i32
|
||||
store i32 %conv, i32* %i, align 4
|
||||
%3 = load i32* %i, align 4
|
||||
ret i32 %3
|
||||
}
|
||||
27
test/CodeGen/Hexagon/convertsptoll.ll
Normal file
27
test/CodeGen/Hexagon/convertsptoll.ll
Normal file
@ -0,0 +1,27 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate conversion from single precision floating point
|
||||
; to 64-bit int value in IEEE complaint mode in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = convert_sf2d(r{{[0-9]+}})
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%i = alloca i64, align 8
|
||||
%a = alloca float, align 4
|
||||
%b = alloca float, align 4
|
||||
%c = alloca float, align 4
|
||||
store i32 0, i32* %retval
|
||||
store float 0x402ECCCCC0000000, float* %a, align 4
|
||||
store float 0x4022333340000000, float* %b, align 4
|
||||
%0 = load float* %a, align 4
|
||||
%1 = load float* %b, align 4
|
||||
%add = fadd float %0, %1
|
||||
store float %add, float* %c, align 4
|
||||
%2 = load float* %c, align 4
|
||||
%conv = fptosi float %2 to i64
|
||||
store i64 %conv, i64* %i, align 8
|
||||
%3 = load i64* %i, align 8
|
||||
%conv1 = trunc i64 %3 to i32
|
||||
ret i32 %conv1
|
||||
}
|
||||
19
test/CodeGen/Hexagon/dadd.ll
Normal file
19
test/CodeGen/Hexagon/dadd.ll
Normal file
@ -0,0 +1,19 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate double precision floating point add in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfadd(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
|
||||
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%a = alloca double, align 8
|
||||
%b = alloca double, align 8
|
||||
%c = alloca double, align 8
|
||||
store double 1.540000e+01, double* %a, align 8
|
||||
store double 9.100000e+00, double* %b, align 8
|
||||
%0 = load double* %a, align 8
|
||||
%1 = load double* %b, align 8
|
||||
%add = fadd double %0, %1
|
||||
store double %add, double* %c, align 8
|
||||
ret i32 0
|
||||
}
|
||||
18
test/CodeGen/Hexagon/dmul.ll
Normal file
18
test/CodeGen/Hexagon/dmul.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate double precision floating point multiply in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpy(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%a = alloca double, align 8
|
||||
%b = alloca double, align 8
|
||||
%c = alloca double, align 8
|
||||
store double 1.540000e+01, double* %a, align 8
|
||||
store double 9.100000e+00, double* %b, align 8
|
||||
%0 = load double* %b, align 8
|
||||
%1 = load double* %a, align 8
|
||||
%mul = fmul double %0, %1
|
||||
store double %mul, double* %c, align 8
|
||||
ret i32 0
|
||||
}
|
||||
26
test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
Normal file
26
test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s
|
||||
; Check that we generate conversion from double precision floating point
|
||||
; to 32-bit int value in IEEE rounding to the nearest mode in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}})
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%i = alloca i32, align 4
|
||||
%a = alloca double, align 8
|
||||
%b = alloca double, align 8
|
||||
%c = alloca double, align 8
|
||||
store i32 0, i32* %retval
|
||||
store double 1.540000e+01, double* %a, align 8
|
||||
store double 9.100000e+00, double* %b, align 8
|
||||
%0 = load double* %a, align 8
|
||||
%1 = load double* %b, align 8
|
||||
%add = fadd double %0, %1
|
||||
store double %add, double* %c, align 8
|
||||
%2 = load double* %c, align 8
|
||||
%conv = fptosi double %2 to i32
|
||||
store i32 %conv, i32* %i, align 4
|
||||
%3 = load i32* %i, align 4
|
||||
ret i32 %3
|
||||
}
|
||||
18
test/CodeGen/Hexagon/dsub.ll
Normal file
18
test/CodeGen/Hexagon/dsub.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate double precision floating point subtract in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfsub(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%a = alloca double, align 8
|
||||
%b = alloca double, align 8
|
||||
%c = alloca double, align 8
|
||||
store double 1.540000e+01, double* %a, align 8
|
||||
store double 9.100000e+00, double* %b, align 8
|
||||
%0 = load double* %b, align 8
|
||||
%1 = load double* %a, align 8
|
||||
%sub = fsub double %0, %1
|
||||
store double %sub, double* %c, align 8
|
||||
ret i32 0
|
||||
}
|
||||
18
test/CodeGen/Hexagon/fadd.ll
Normal file
18
test/CodeGen/Hexagon/fadd.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate sp floating point add in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}})
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%a = alloca float, align 4
|
||||
%b = alloca float, align 4
|
||||
%c = alloca float, align 4
|
||||
store float 0x402ECCCCC0000000, float* %a, align 4
|
||||
store float 0x4022333340000000, float* %b, align 4
|
||||
%0 = load float* %a, align 4
|
||||
%1 = load float* %b, align 4
|
||||
%add = fadd float %0, %1
|
||||
store float %add, float* %c, align 4
|
||||
ret i32 0
|
||||
}
|
||||
37
test/CodeGen/Hexagon/fcmp.ll
Normal file
37
test/CodeGen/Hexagon/fcmp.ll
Normal file
@ -0,0 +1,37 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate floating point compare in V5
|
||||
|
||||
; CHECK: p{{[0-2]+}} = sfcmp.{{.}}
|
||||
|
||||
define i32 @foo(float %y) nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%y.addr = alloca float, align 4
|
||||
store float %y, float* %y.addr, align 4
|
||||
%0 = load float* %y.addr, align 4
|
||||
%cmp = fcmp ogt float %0, 0x406AD7EFA0000000
|
||||
br i1 %cmp, label %if.then, label %if.else
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* %retval
|
||||
br label %return
|
||||
|
||||
if.else: ; preds = %entry
|
||||
store i32 2, i32* %retval
|
||||
br label %return
|
||||
|
||||
return: ; preds = %if.else, %if.then
|
||||
%1 = load i32* %retval
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%a = alloca float, align 4
|
||||
store i32 0, i32* %retval
|
||||
store float 0x40012E0A00000000, float* %a, align 4
|
||||
%0 = load float* %a, align 4
|
||||
%call = call i32 @foo(float %0)
|
||||
ret i32 %call
|
||||
}
|
||||
23
test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
Normal file
23
test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
Normal file
@ -0,0 +1,23 @@
|
||||
; RUN: true
|
||||
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; CHECK: __hexagon_addsf3
|
||||
; CHECK: __hexagon_subsf3
|
||||
|
||||
define void @foo(float* %acc, float %num, float %num2) nounwind {
|
||||
entry:
|
||||
%acc.addr = alloca float*, align 4
|
||||
%num.addr = alloca float, align 4
|
||||
%num2.addr = alloca float, align 4
|
||||
store float* %acc, float** %acc.addr, align 4
|
||||
store float %num, float* %num.addr, align 4
|
||||
store float %num2, float* %num2.addr, align 4
|
||||
%0 = load float** %acc.addr, align 4
|
||||
%1 = load float* %0
|
||||
%2 = load float* %num.addr, align 4
|
||||
%add = fadd float %1, %2
|
||||
%3 = load float* %num2.addr, align 4
|
||||
%sub = fsub float %add, %3
|
||||
%4 = load float** %acc.addr, align 4
|
||||
store float %sub, float* %4
|
||||
ret void
|
||||
}
|
||||
19
test/CodeGen/Hexagon/fmul.ll
Normal file
19
test/CodeGen/Hexagon/fmul.ll
Normal file
@ -0,0 +1,19 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate single precision floating point multiply in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}}, r{{[0-9]+}})
|
||||
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%a = alloca float, align 4
|
||||
%b = alloca float, align 4
|
||||
%c = alloca float, align 4
|
||||
store float 0x402ECCCCC0000000, float* %a, align 4
|
||||
store float 0x4022333340000000, float* %b, align 4
|
||||
%0 = load float* %b, align 4
|
||||
%1 = load float* %a, align 4
|
||||
%mul = fmul float %0, %1
|
||||
store float %mul, float* %c, align 4
|
||||
ret i32 0
|
||||
}
|
||||
18
test/CodeGen/Hexagon/fsub.ll
Normal file
18
test/CodeGen/Hexagon/fsub.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Check that we generate sp floating point subtract in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}}, r{{[0-9]+}})
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%a = alloca float, align 4
|
||||
%b = alloca float, align 4
|
||||
%c = alloca float, align 4
|
||||
store float 0x402ECCCCC0000000, float* %a, align 4
|
||||
store float 0x4022333340000000, float* %b, align 4
|
||||
%0 = load float* %b, align 4
|
||||
%1 = load float* %a, align 4
|
||||
%sub = fsub float %0, %1
|
||||
store float %sub, float* %c, align 4
|
||||
ret i32 0
|
||||
}
|
||||
15
test/CodeGen/Hexagon/opt-fabs.ll
Normal file
15
test/CodeGen/Hexagon/opt-fabs.ll
Normal file
@ -0,0 +1,15 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Optimize fabsf to clrbit in V5.
|
||||
|
||||
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
|
||||
|
||||
define float @my_fabsf(float %x) nounwind {
|
||||
entry:
|
||||
%x.addr = alloca float, align 4
|
||||
store float %x, float* %x.addr, align 4
|
||||
%0 = load float* %x.addr, align 4
|
||||
%call = call float @fabsf(float %0)
|
||||
ret float %call
|
||||
}
|
||||
|
||||
declare float @fabsf(float)
|
||||
26
test/CodeGen/Hexagon/opt-fneg.ll
Normal file
26
test/CodeGen/Hexagon/opt-fneg.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Optimize fneg to togglebit in V5.
|
||||
|
||||
define float @foo(float %x) nounwind {
|
||||
entry:
|
||||
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
|
||||
%x.addr = alloca float, align 4
|
||||
store float %x, float* %x.addr, align 4
|
||||
%0 = load float* %x.addr, align 4
|
||||
%sub = fsub float -0.000000e+00, %0
|
||||
ret float %sub
|
||||
}
|
||||
|
||||
define float @bar(float %x) nounwind {
|
||||
entry:
|
||||
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
|
||||
%sub = fsub float -0.000000e+00, %x
|
||||
ret float %sub
|
||||
}
|
||||
|
||||
define float @baz(float %x) nounwind {
|
||||
entry:
|
||||
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
|
||||
%conv1 = fmul float %x, -1.000000e+00
|
||||
ret float %conv1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user