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This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic 2013-07-18 09:28:35 +00:00
parent fe754512dc
commit 764f6f5125
2 changed files with 16 additions and 0 deletions
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12
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -1268,6 +1268,18 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
// Set the proper register kind.
MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
op->setRegKind(Kind);
if ((Kind == MipsOperand::Kind_CPURegs)
&& (getLexer().is(AsmToken::LParen))) {
// Check if it is indexed addressing operand.
Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
Parser.Lex(); // Eat the parenthesis.
if (parseRegs(Operands,RegKind) != MatchOperand_Success)
return MatchOperand_NoMatch;
if (getLexer().isNot(AsmToken::RParen))
return MatchOperand_NoMatch;
Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
Parser.Lex();
}
return MatchOperand_Success;
}
return MatchOperand_NoMatch;

4
test/MC/Mips/mips-fpu-instructions.s
View File

@ -158,6 +158,8 @@
# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
# CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
# CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00]
# CHECK: luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c]
# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c]
cfc1 $a2,$0
mfc1 $a2,$f7
@ -179,3 +181,5 @@
mtc2 $9, $4, 5
movf $2, $1, $fcc0
movt $2, $1, $fcc0
luxc1 $f0, $a2($a1)
suxc1 $f4, $t8($a1)