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https://github.com/RPCS3/llvm.git
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add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
796c193768
commit
768c65f677
@ -407,6 +407,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setInsertFencesForAtomic(true);
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setSchedulingPreference(Sched::Hybrid);
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computeRegisterProperties();
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}
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@ -56,11 +56,8 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
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unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
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if (Directive == PPC::DIR_440) {
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// Disable the hazard recognizer for now, as it doesn't support
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// bottom-up scheduling.
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//const InstrItineraryData *II = TM->getInstrItineraryData();
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//return new PPCHazardRecognizer440(II, DAG);
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return new ScheduleHazardRecognizer();
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const InstrItineraryData *II = TM->getInstrItineraryData();
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return new PPCHazardRecognizer440(II, DAG);
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}
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else {
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// Disable the hazard recognizer for now, as it doesn't support
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@ -273,6 +273,27 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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return Reserved;
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}
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unsigned
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PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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const unsigned DefaultSafety = 1;
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switch (RC->getID()) {
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default:
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return 0;
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case PPC::G8RCRegClassID:
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case PPC::GPRCRegClassID: {
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unsigned FP = TFI->hasFP(MF) ? 1 : 0;
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return 32 - FP - DefaultSafety;
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}
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case PPC::F8RCRegClassID:
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case PPC::F4RCRegClassID:
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case PPC::VRRCRegClassID:
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return 32 - DefaultSafety;
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}
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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@ -37,6 +37,9 @@ public:
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const;
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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@ -12,10 +12,9 @@ target triple = "powerpc-unknown-freebsd9.0"
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define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
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entry:
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%x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
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; CHECK: lbz 4, 0(3)
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; CHECK-NEXT: rlwinm 5, 4, 0, 31, 31
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; CHECK-NEXT: cmplwi 0, 5, 0
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; CHECK-NEXT: addi 5, 4, 1
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; CHECK: addi 5, 4, 1
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; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
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; CHECK-NEXT: cmplwi 0, 6, 0
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; CHECK-NEXT: stw 3, -4(1)
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; CHECK-NEXT: stw 5, -8(1)
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; CHECK-NEXT: stw 4, -12(1)
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@ -25,138 +24,137 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
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; CHECK-NEXT: stw 3, -8(1)
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; CHECK-NEXT: .LBB0_2: # %entry
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; CHECK-NEXT: lwz 3, -8(1)
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; CHECK-NEXT: slwi 4, 3, 2
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; CHECK-NEXT: addi 4, 3, 2
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: lwz 6, 4(5)
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; CHECK-NEXT: lwz 7, 8(5)
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; CHECK-NEXT: add 4, 7, 4
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; CHECK-NEXT: stb 4, 0(5)
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: addi 4, 6, 4
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; CHECK-NEXT: mr 8, 6
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; CHECK-NEXT: stw 7, -16(1)
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; CHECK-NEXT: stw 4, -20(1)
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; CHECK-NEXT: stw 3, -24(1)
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; CHECK-NEXT: stw 8, -28(1)
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; CHECK-NEXT: stw 6, -32(1)
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -16(1)
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; CHECK-NEXT: stw 3, -20(1)
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; CHECK-NEXT: stw 4, -24(1)
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; CHECK-NEXT: stw 6, -28(1)
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; CHECK-NEXT: stw 0, -36(1)
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; CHECK-NEXT: blt 0, .LBB0_4
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; CHECK-NEXT: # BB#3: # %entry
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; CHECK-NEXT: lwz 3, -28(1)
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; CHECK-NEXT: stw 3, -24(1)
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; CHECK-NEXT: lwz 3, -20(1)
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; CHECK-NEXT: stw 3, -28(1)
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; CHECK-NEXT: .LBB0_4: # %entry
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; CHECK-NEXT: lwz 3, -28(1)
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; CHECK-NEXT: lwz 4, -4(1)
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; CHECK-NEXT: stw 3, 4(4)
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store i64 %x, i64* @var1, align 8
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; CHECK-NEXT: lwz 3, -24(1)
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; CHECK-NEXT: lwz 4, -28(1)
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; CHECK-NEXT: addi 5, 4, 4
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; CHECK-NEXT: lwz 0, -16(1)
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; CHECK-NEXT: slwi 5, 3, 2
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; CHECK-NEXT: lwz 6, -16(1)
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; CHECK-NEXT: add 5, 6, 5
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; CHECK-NEXT: lwz 0, -36(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 4, -32(1)
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; CHECK-NEXT: stw 5, -36(1)
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; CHECK-NEXT: stw 3, -40(1)
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; CHECK-NEXT: stw 5, -40(1)
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; CHECK-NEXT: blt 0, .LBB0_6
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; CHECK-NEXT: # BB#5: # %entry
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; CHECK-NEXT: lwz 3, -36(1)
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; CHECK-NEXT: stw 3, -32(1)
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; CHECK-NEXT: .LBB0_6: # %entry
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; CHECK-NEXT: lwz 3, -32(1)
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; CHECK-NEXT: lwz 4, -20(1)
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; CHECK-NEXT: addi 5, 4, 2
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; CHECK-NEXT: lwz 6, -4(1)
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; CHECK-NEXT: stb 5, 0(6)
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; CHECK-NEXT: stw 3, 4(6)
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store i64 %x, i64* @var1, align 8
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; CHECK-NEXT: stw 3, -40(1)
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; CHECK-NEXT: .LBB0_6: # %entry
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; CHECK-NEXT: lwz 3, -40(1)
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; CHECK-NEXT: lwz 5, 0(3)
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; CHECK-NEXT: lwz 7, 4(3)
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; CHECK-NEXT: lis 8, var1@ha
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; CHECK-NEXT: la 9, var1@l(8)
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; CHECK-NEXT: stw 7, 4(9)
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; CHECK-NEXT: stw 5, var1@l(8)
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; CHECK-NEXT: lwz 4, 0(3)
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; CHECK-NEXT: lwz 3, 4(3)
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; CHECK-NEXT: lis 5, var1@ha
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; CHECK-NEXT: la 6, var1@l(5)
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; CHECK-NEXT: stw 3, 4(6)
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; CHECK-NEXT: stw 4, var1@l(5)
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; CHECK-NEXT: lwz 3, -4(1)
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%y = va_arg %struct.__va_list_tag* %ap, double; From f1
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; CHECK-NEXT: lbz 5, 1(6)
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; CHECK-NEXT: lwz 7, 4(6)
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; CHECK-NEXT: lwz 8, 8(6)
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; CHECK-NEXT: slwi 9, 5, 3
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; CHECK-NEXT: add 8, 8, 9
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; CHECK-NEXT: cmpwi 0, 5, 8
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; CHECK-NEXT: addi 9, 7, 8
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; CHECK-NEXT: mr 10, 7
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; CHECK-NEXT: stw 9, -44(1)
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; CHECK-NEXT: lbz 4, 1(3)
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; CHECK-NEXT: lwz 5, 4(3)
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; CHECK-NEXT: lwz 6, 8(3)
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; CHECK-NEXT: addi 7, 4, 1
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; CHECK-NEXT: stb 7, 1(3)
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; CHECK-NEXT: cmpwi 0, 4, 8
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; CHECK-NEXT: addi 7, 5, 8
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; CHECK-NEXT: mr 8, 5
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; CHECK-NEXT: stw 5, -44(1)
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; CHECK-NEXT: stw 7, -48(1)
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; CHECK-NEXT: stw 4, -52(1)
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; CHECK-NEXT: stw 6, -56(1)
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; CHECK-NEXT: stw 8, -60(1)
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -52(1)
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; CHECK-NEXT: stw 5, -56(1)
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; CHECK-NEXT: stw 10, -60(1)
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; CHECK-NEXT: stw 8, -64(1)
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; CHECK-NEXT: stw 0, -64(1)
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; CHECK-NEXT: blt 0, .LBB0_8
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; CHECK-NEXT: # BB#7: # %entry
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; CHECK-NEXT: lwz 3, -44(1)
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; CHECK-NEXT: lwz 3, -48(1)
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; CHECK-NEXT: stw 3, -60(1)
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; CHECK-NEXT: .LBB0_8: # %entry
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; CHECK-NEXT: lwz 3, -60(1)
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; CHECK-NEXT: lwz 4, -64(1)
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; CHECK-NEXT: addi 4, 4, 32
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; CHECK-NEXT: lwz 0, -52(1)
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; CHECK-NEXT: lwz 4, -4(1)
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; CHECK-NEXT: stw 3, 4(4)
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; CHECK-NEXT: lwz 3, -52(1)
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; CHECK-NEXT: slwi 5, 3, 3
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; CHECK-NEXT: lwz 6, -56(1)
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; CHECK-NEXT: add 5, 6, 5
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; CHECK-NEXT: addi 5, 5, 32
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; CHECK-NEXT: lwz 0, -64(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 4, -68(1)
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; CHECK-NEXT: stw 3, -72(1)
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; CHECK-NEXT: stw 5, -68(1)
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; CHECK-NEXT: blt 0, .LBB0_10
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; CHECK-NEXT: # BB#9: # %entry
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; CHECK-NEXT: lwz 3, -48(1)
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; CHECK-NEXT: lwz 3, -44(1)
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; CHECK-NEXT: stw 3, -68(1)
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; CHECK-NEXT: .LBB0_10: # %entry
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; CHECK-NEXT: lwz 3, -68(1)
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; CHECK-NEXT: lwz 4, -56(1)
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; CHECK-NEXT: addi 5, 4, 1
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; CHECK-NEXT: lwz 6, -4(1)
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; CHECK-NEXT: stb 5, 1(6)
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; CHECK-NEXT: lwz 5, -72(1)
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; CHECK-NEXT: stw 5, 4(6)
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; CHECK-NEXT: lfd 0, 0(3)
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store double %y, double* @var2, align 8
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; CHECK-NEXT: lis 3, var2@ha
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; CHECK-NEXT: stfd 0, var2@l(3)
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%z = va_arg %struct.__va_list_tag* %ap, i32; From r7
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; CHECK-NEXT: lbz 3, 0(6)
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; CHECK-NEXT: lwz 5, 4(6)
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; CHECK-NEXT: lwz 7, 8(6)
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; CHECK-NEXT: slwi 8, 3, 2
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; CHECK-NEXT: add 7, 7, 8
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: addi 8, 5, 4
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; CHECK-NEXT: mr 9, 5
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; CHECK-NEXT: stw 3, -76(1)
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; CHECK-NEXT: stw 7, -80(1)
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; CHECK-NEXT: stw 8, -84(1)
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; CHECK-NEXT: stw 5, -88(1)
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; CHECK-NEXT: stw 9, -92(1)
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; CHECK-NEXT: lwz 3, -4(1)
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; CHECK-NEXT: lbz 4, 0(3)
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; CHECK-NEXT: lwz 5, 4(3)
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; CHECK-NEXT: lwz 6, 8(3)
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; CHECK-NEXT: addi 7, 4, 1
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; CHECK-NEXT: stb 7, 0(3)
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; CHECK-NEXT: cmpwi 0, 4, 8
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; CHECK-NEXT: addi 7, 5, 4
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; CHECK-NEXT: mr 8, 5
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; CHECK-NEXT: stw 4, -72(1)
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; CHECK-NEXT: stw 6, -76(1)
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -96(1)
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; CHECK-NEXT: stw 0, -80(1)
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; CHECK-NEXT: stw 5, -84(1)
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; CHECK-NEXT: stw 8, -88(1)
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; CHECK-NEXT: stw 7, -92(1)
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; CHECK-NEXT: blt 0, .LBB0_12
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; CHECK-NEXT: # BB#11: # %entry
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; CHECK-NEXT: lwz 3, -84(1)
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; CHECK-NEXT: stw 3, -92(1)
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; CHECK-NEXT: .LBB0_12: # %entry
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; CHECK-NEXT: lwz 3, -92(1)
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; CHECK-NEXT: lwz 4, -80(1)
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; CHECK-NEXT: lwz 0, -96(1)
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; CHECK-NEXT: stw 3, -88(1)
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; CHECK-NEXT: .LBB0_12: # %entry
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; CHECK-NEXT: lwz 3, -88(1)
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; CHECK-NEXT: lwz 4, -4(1)
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; CHECK-NEXT: stw 3, 4(4)
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; CHECK-NEXT: lwz 3, -72(1)
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; CHECK-NEXT: slwi 5, 3, 2
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; CHECK-NEXT: lwz 6, -76(1)
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; CHECK-NEXT: add 5, 6, 5
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; CHECK-NEXT: lwz 0, -80(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 3, -100(1)
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; CHECK-NEXT: stw 4, -104(1)
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; CHECK-NEXT: stw 5, -96(1)
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; CHECK-NEXT: blt 0, .LBB0_14
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; CHECK-NEXT: # BB#13: # %entry
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; CHECK-NEXT: lwz 3, -88(1)
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; CHECK-NEXT: stw 3, -104(1)
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; CHECK-NEXT: lwz 3, -84(1)
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; CHECK-NEXT: stw 3, -96(1)
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; CHECK-NEXT: .LBB0_14: # %entry
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; CHECK-NEXT: lwz 3, -104(1)
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; CHECK-NEXT: lwz 4, -76(1)
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; CHECK-NEXT: addi 5, 4, 1
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; CHECK-NEXT: lwz 6, -4(1)
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; CHECK-NEXT: stb 5, 0(6)
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; CHECK-NEXT: lwz 5, -100(1)
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; CHECK-NEXT: stw 5, 4(6)
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; CHECK-NEXT: lwz 3, -96(1)
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; CHECK-NEXT: lwz 3, 0(3)
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store i32 %z, i32* @var3, align 4
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; CHECK-NEXT: lis 5, var3@ha
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; CHECK-NEXT: stw 3, var3@l(5)
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; CHECK-NEXT: lis 4, var3@ha
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; CHECK-NEXT: stw 3, var3@l(4)
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; CHECK-NEXT: lwz 3, -4(1)
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ret void
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; CHECK-NEXT: stw 6, -108(1)
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; CHECK-NEXT: stw 3, -100(1)
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; CHECK-NEXT: blr
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}
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