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DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)).

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PR15948.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181597 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-05-10 14:09:52 +00:00
parent 51dab6e394
commit 768ebcdf63
2 changed files with 12 additions and 2 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3464,8 +3464,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
N0->getOperand(1) == N1) {
SDValue X = N0->getOperand(0);
SDValue NotX = DAG.getNode(ISD::XOR, X.getDebugLoc(), VT, X,
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
SDValue NotX = DAG.getNOT(X.getDebugLoc(), X, VT);
AddToWorkList(NotX.getNode());
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NotX, N1);
}

11
test/CodeGen/X86/xor.ll
View File

@ -154,3 +154,14 @@ define i32 @test9(i32 %a) nounwind {
; X32: notl [[REG:%[a-z]+]]
; X32: andl {{.*}}[[REG:%[a-z]+]]
}
; PR15948
define <4 x i32> @test10(<4 x i32> %a) nounwind {
%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
ret <4 x i32> %2
; X64: test10:
; X64: andnps
; X32: test10:
; X32: andnps
}