RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-24 04:56:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add constant pool support, including folding into addresses.

Browse Source 
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24813 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-18 02:37:35 +00:00
parent e1389ad43a
commit 76acc872b3
6 changed files with 48 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -185,8 +185,20 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
printOperand(MI, opNum);
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if ((OpTy == MachineOperand::MO_VirtualRegister ||
OpTy == MachineOperand::MO_MachineRegister) &&
MI->getOperand(opNum+1).getReg() == V8::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
OpTy == MachineOperand::MO_UnextendedImmed) &&
MI->getOperand(opNum+1).getImmedValue() == 0)
return; // don't print "+0"
O << "+";
if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
if (OpTy == MachineOperand::MO_GlobalAddress ||
OpTy == MachineOperand::MO_ConstantPoolIndex) {
O << "%lo(";
printOperand(MI, opNum+1);
O << ")";

8
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -75,6 +75,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
@ -251,6 +252,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
case ISD::ConstantPool: {
Constant *C = cast<ConstantPoolSDNode>(Op)->get();
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
}
}

4
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -660,6 +660,8 @@ def : Pat<(i32 simm13:$val),
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
// Global addresses
// Global addresses, constant pool entries
def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;

14
lib/Target/SparcV8/SparcV8AsmPrinter.cpp
View File

@ -185,8 +185,20 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
printOperand(MI, opNum);
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if ((OpTy == MachineOperand::MO_VirtualRegister ||
OpTy == MachineOperand::MO_MachineRegister) &&
MI->getOperand(opNum+1).getReg() == V8::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
OpTy == MachineOperand::MO_UnextendedImmed) &&
MI->getOperand(opNum+1).getImmedValue() == 0)
return; // don't print "+0"
O << "+";
if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
if (OpTy == MachineOperand::MO_GlobalAddress ||
OpTy == MachineOperand::MO_ConstantPoolIndex) {
O << "%lo(";
printOperand(MI, opNum+1);
O << ")";

8
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -75,6 +75,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
@ -251,6 +252,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
case ISD::ConstantPool: {
Constant *C = cast<ConstantPoolSDNode>(Op)->get();
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
}
}

4
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -660,6 +660,8 @@ def : Pat<(i32 simm13:$val),
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
// Global addresses
// Global addresses, constant pool entries
def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;