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Enable generating PPC pre-increment (r+imm) instructions by default.

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It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157911 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2012-06-04 02:21:00 +00:00
parent 761cb06756
commit 77838f9ca9
3 changed files with 6 additions and 8 deletions
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8
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -51,9 +51,8 @@ static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
cl::desc("enable preincrement load/store generation on PPC (experimental)"),
cl::Hidden);
static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
if (TM.getSubtargetImpl()->isDarwin())
@ -1084,8 +1083,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const {
// Disabled by default for now.
if (!EnablePPCPreinc) return false;
if (DisablePPCPreinc) return false;
SDValue Ptr;
EVT VT;

4
test/CodeGen/PowerPC/mem_update.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=ppc32 -enable-ppc-preinc | \
; RUN: llc < %s -march=ppc32 | \
; RUN: not grep addi
; RUN: llc < %s -march=ppc64 -enable-ppc-preinc | \
; RUN: llc < %s -march=ppc64 | \
; RUN: not grep addi
@Glob = global i64 4

2
test/CodeGen/PowerPC/stwu8.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -enable-ppc-preinc < %s | FileCheck %s
; RUN: llc < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"