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[DAGCombiner] Remove extra bitcasts surrounding vector shuffles

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Patch to remove extra bitcasts from shuffles, this is often a legacy of XformToShuffleWithZero being used to combine bitmaskings (of float vectors bitcast to integer vectors) into shuffles: bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1)

Differential Revision: http://reviews.llvm.org/D9097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235578 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2015-04-23 08:43:13 +00:00
parent 9311f5b6fe
commit 77aa4a8c4d
2 changed files with 109 additions and 0 deletions
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45
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6934,6 +6934,51 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
return CombineLD; return CombineLD;
} }
// Remove double bitcasts from shuffles - this is often a legacy of
// XformToShuffleWithZero being used to combine bitmaskings (of
// float vectors bitcast to integer vectors) into shuffles.
// bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1)
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() &&
N0->getOpcode() == ISD::VECTOR_SHUFFLE &&
VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() &&
!(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) {
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0);
// If operands are a bitcast, peek through if it casts the original VT.
// If operands are a UNDEF or constant, just bitcast back to original VT.
auto PeekThroughBitcast = [&](SDValue Op) {
if (Op.getOpcode() == ISD::BITCAST &&
Op.getOperand(0)->getValueType(0) == VT)
return SDValue(Op.getOperand(0));
if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()))
return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
return SDValue();
};
SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
if (!(SV0 && SV1))
return SDValue();
int MaskScale =
VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();
SmallVector<int, 8> NewMask;
for (int M : SVN->getMask())
for (int i = 0; i != MaskScale; ++i)
NewMask.push_back(M < 0 ? -1 : M * MaskScale + i);
bool LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
if (!LegalMask) {
std::swap(SV0, SV1);
ShuffleVectorSDNode::commuteMask(NewMask);
LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
}
if (LegalMask)
return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask);
}
return SDValue(); return SDValue();
} }

64
test/CodeGen/X86/combine-or.ll
View File

@ -277,6 +277,70 @@ define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
ret <2 x i64> %or ret <2 x i64> %or
} }
; Verify that the dag-combiner keeps the correct domain for float/double vectors
; bitcast to use the mask-or blend combine.
define <2 x double> @test22(<2 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: test22:
; CHECK: # BB#0:
; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; CHECK-NEXT: retq
%bc1 = bitcast <2 x double> %a0 to <2 x i64>
%bc2 = bitcast <2 x double> %a1 to <2 x i64>
%and1 = and <2 x i64> %bc1, <i64 0, i64 -1>
%and2 = and <2 x i64> %bc2, <i64 -1, i64 0>
%or = or <2 x i64> %and1, %and2
%bc3 = bitcast <2 x i64> %or to <2 x double>
ret <2 x double> %bc3
}
define <4 x float> @test23(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: test23:
; CHECK: # BB#0:
; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %a0 to <4 x i32>
%bc2 = bitcast <4 x float> %a1 to <4 x i32>
%and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0>
%and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1>
%or = or <4 x i32> %and1, %and2
%bc3 = bitcast <4 x i32> %or to <4 x float>
ret <4 x float> %bc3
}
define <4 x float> @test24(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: test24:
; CHECK: # BB#0:
; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %a0 to <2 x i64>
%bc2 = bitcast <4 x float> %a1 to <2 x i64>
%and1 = and <2 x i64> %bc1, <i64 0, i64 -1>
%and2 = and <2 x i64> %bc2, <i64 -1, i64 0>
%or = or <2 x i64> %and1, %and2
%bc3 = bitcast <2 x i64> %or to <4 x float>
ret <4 x float> %bc3
}
define <4 x float> @test25(<4 x float> %a0) {
; CHECK-LABEL: test25:
; CHECK: # BB#0:
; CHECK-NEXT: blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3]
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %a0 to <4 x i32>
%bc2 = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32>
%and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0>
%and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1>
%or = or <4 x i32> %and1, %and2
%bc3 = bitcast <4 x i32> %or to <4 x float>
ret <4 x float> %bc3
}
; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle ; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle
; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to ; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to
; handle legal vector value types. ; handle legal vector value types.