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[Hexagon] Reset spill alignment when variable-sized objects are present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302029 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -869,6 +869,9 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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unsigned KillFlag = getKillRegState(isKill);
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bool HasAlloca = MFI.hasVarSizedObjects();
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const auto &HST = MF.getSubtarget<HexagonSubtarget>();
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const HexagonFrameLowering &HFI = *HST.getFrameLowering();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
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@ -899,24 +902,36 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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.addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, KillFlag).addMemOperand(MMO);
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} else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
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: Hexagon::V6_vS32b_ai_128B;
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BuildMI(MBB, I, DL, get(Opc))
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.addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, KillFlag).addMemOperand(MMO);
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} else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
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: Hexagon::V6_vS32b_ai;
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BuildMI(MBB, I, DL, get(Opc))
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.addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, KillFlag).addMemOperand(MMO);
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} else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
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: Hexagon::PS_vstorerw_ai;
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BuildMI(MBB, I, DL, get(Opc))
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.addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, KillFlag).addMemOperand(MMO);
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} else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
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: Hexagon::PS_vstorerw_ai_128B;
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BuildMI(MBB, I, DL, get(Opc))
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@ -935,6 +950,9 @@ void HexagonInstrInfo::loadRegFromStackSlot(
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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bool HasAlloca = MFI.hasVarSizedObjects();
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const auto &HST = MF.getSubtarget<HexagonSubtarget>();
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const HexagonFrameLowering &HFI = *HST.getFrameLowering();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
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@ -959,21 +977,33 @@ void HexagonInstrInfo::loadRegFromStackSlot(
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BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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} else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
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: Hexagon::PS_vloadrw_ai_128B;
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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} else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
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: Hexagon::V6_vL32b_ai_128B;
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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} else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
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: Hexagon::V6_vL32b_ai;
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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} else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
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// If there are variable-sized objects, spills will not be aligned.
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if (HasAlloca)
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Align = HFI.getStackAlignment();
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unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
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: Hexagon::PS_vloadrw_ai;
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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