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misched: Make ScheduleDAGInstrs use the TargetSchedule interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164153 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -52,6 +52,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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DbgValues.clear();
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assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
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"Virtual registers must be removed prior to PostRA scheduling");
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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SchedModel.init(*ST.getSchedModel(), &ST, TII);
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}
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/// getUnderlyingObjectFromInt - This is the function that does the work of
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@ -274,15 +277,13 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
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// perform its own adjustments.
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SDep dep(SU, SDep::Data, LDataLatency, *Alias);
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if (!UnitLatencies) {
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unsigned Latency =
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TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx,
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(UseOp < 0 ? 0 : UseMI), UseOp);
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dep.setLatency(Latency);
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unsigned MinLatency =
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TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx,
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(UseOp < 0 ? 0 : UseMI), UseOp,
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/*FindMin=*/true);
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dep.setMinLatency(MinLatency);
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MachineInstr *RegUse = UseOp < 0 ? 0 : UseMI;
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dep.setLatency(
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SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
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RegUse, UseOp, /*FindMin=*/false));
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dep.setMinLatency(
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SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
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RegUse, UseOp, /*FindMin=*/true));
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ST.adjustSchedDependency(SU, UseSU, dep);
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}
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@ -477,13 +478,10 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
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// Adjust the dependence latency using operand def/use information, then
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// allow the target to perform its own adjustments.
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int DefOp = Def->findRegisterDefOperandIdx(Reg);
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unsigned Latency =
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TII->computeOperandLatency(InstrItins, Def, DefOp, MI, OperIdx);
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dep.setLatency(Latency);
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unsigned MinLatency =
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TII->computeOperandLatency(InstrItins, Def, DefOp, MI, OperIdx,
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/*FindMin=*/true);
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dep.setMinLatency(MinLatency);
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dep.setLatency(
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SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false));
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dep.setMinLatency(
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SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true));
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
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