From 78432feff87d20d15466952c59969ea410ae85bb Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 17 Nov 2005 02:01:55 +0000 Subject: [PATCH] Add patterns for some 16-bit immediate instructions, patch contributed by Evan Cheng. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24384 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrInfo.td | 65 +++++++++++++++++++--------------- 1 file changed, 37 insertions(+), 28 deletions(-) diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 66ab58a2e0d..248b043253b 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -133,8 +133,10 @@ class I o, Format f, dag ops, string asm> : X86Inst; class Ii8 o, Format f, dag ops, string asm> : X86Inst; -class Ii16 o, Format f, dag ops, string asm> - : X86Inst; +class Ii16 o, Format f, dag ops, string asm, list pattern> + : X86Inst { + let Pattern = pattern; +} class Ii32 o, Format f, dag ops, string asm, list pattern> : X86Inst { let Pattern = pattern; @@ -164,7 +166,7 @@ let isTerminator = 1 in let isTerminator = 1, isReturn = 1, isBarrier = 1 in def RET : I<0xC3, RawFrm, (ops), "ret">; let isTerminator = 1, isReturn = 1, isBarrier = 1 in - def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt">; + def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in @@ -292,11 +294,11 @@ def IN32rr : I<0xED, RawFrm, (ops), "in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>; def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port), - "in{b} {$port, %al|%AL, $port}">, Imp<[], [AL]>; + "in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>; def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), - "in{w} {$port, %ax|%AX, $port}">, Imp<[], [AX]>, OpSize; + "in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize; def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), - "in{l} {$port, %eax|%EAX, $port}">, Imp<[],[EAX]>; + "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>; def OUT8rr : I<0xEE, RawFrm, (ops), "out{b} {%al, %dx|%DX, %AL}">, Imp<[DX, AL], []>; @@ -306,11 +308,11 @@ def OUT32rr : I<0xEF, RawFrm, (ops), "out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>; def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port), - "out{b} {%al, $port|$port, %AL}">, Imp<[AL], []>; + "out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>; def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), - "out{w} {%ax, $port|$port, %AX}">, Imp<[AX], []>, OpSize; + "out{w} {%ax, $port|$port, %AX}", []>, Imp<[AX], []>, OpSize; def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), - "out{l} {%eax, $port|$port, %EAX}">, Imp<[EAX], []>; + "out{l} {%eax, $port|$port, %EAX}", []>, Imp<[EAX], []>; //===----------------------------------------------------------------------===// // Move Instructions... @@ -324,13 +326,14 @@ def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}">; def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), - "mov{w} {$src, $dst|$dst, $src}">, OpSize; + "mov{w} {$src, $dst|$dst, $src}", [(set R16:$dst, imm:$src)]>, + OpSize; def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", [(set R32:$dst, imm:$src)]>; def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}">; def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), - "mov{w} {$src, $dst|$dst, $src}">, OpSize; + "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", []>; @@ -676,7 +679,8 @@ def AND8ri : Ii8<0x80, MRM4r, "and{b} {$src2, $dst|$dst, $src2}">; def AND16ri : Ii16<0x81, MRM4r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "and{w} {$src2, $dst|$dst, $src2}">, OpSize; + "and{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize; def AND32ri : Ii32<0x81, MRM4r, (ops R32:$dst, R32:$src1, i32imm:$src2), "and{l} {$src2, $dst|$dst, $src2}", @@ -703,7 +707,7 @@ let isTwoAddress = 0 in { "and{b} {$src, $dst|$dst, $src}">; def AND16mi : Ii16<0x81, MRM4m, (ops i16mem:$dst, i16imm:$src), - "and{w} {$src, $dst|$dst, $src}">, OpSize; + "and{w} {$src, $dst|$dst, $src}", []>, OpSize; def AND32mi : Ii32<0x81, MRM4m, (ops i32mem:$dst, i32imm:$src), "and{l} {$src, $dst|$dst, $src}", []>; @@ -734,7 +738,8 @@ def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), "or{b} {$src2, $dst|$dst, $src2}">; def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "or{w} {$src2, $dst|$dst, $src2}">, OpSize; + "or{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize; def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), "or{l} {$src2, $dst|$dst, $src2}", [(set R32:$dst, (or R32:$src1, imm:$src2))]>; @@ -753,7 +758,7 @@ let isTwoAddress = 0 in { def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), "or{b} {$src, $dst|$dst, $src}">; def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), - "or{w} {$src, $dst|$dst, $src}">, OpSize; + "or{w} {$src, $dst|$dst, $src}", []>, OpSize; def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), "or{l} {$src, $dst|$dst, $src}", []>; def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src), @@ -790,7 +795,8 @@ def XOR8ri : Ii8<0x80, MRM6r, "xor{b} {$src2, $dst|$dst, $src2}">; def XOR16ri : Ii16<0x81, MRM6r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; + "xor{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize; def XOR32ri : Ii32<0x81, MRM6r, (ops R32:$dst, R32:$src1, i32imm:$src2), "xor{l} {$src2, $dst|$dst, $src2}", @@ -816,7 +822,7 @@ let isTwoAddress = 0 in { "xor{b} {$src, $dst|$dst, $src}">; def XOR16mi : Ii16<0x81, MRM6m, (ops i16mem:$dst, i16imm:$src), - "xor{w} {$src, $dst|$dst, $src}">, OpSize; + "xor{w} {$src, $dst|$dst, $src}", []>, OpSize; def XOR32mi : Ii32<0x81, MRM6m, (ops i32mem:$dst, i32imm:$src), "xor{l} {$src, $dst|$dst, $src}", []>; @@ -1065,7 +1071,8 @@ def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + "add{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize; def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set R32:$dst, (add R32:$src1, imm:$src2))]>; @@ -1086,7 +1093,7 @@ let isTwoAddress = 0 in { def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), "add{b} {$src2, $dst|$dst, $src2}">; def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), - "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", []>; def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2), @@ -1131,7 +1138,8 @@ def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}">; def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + "sub{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize; def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", [(set R32:$dst, (sub R32:$src1, imm:$src2))]>; @@ -1149,7 +1157,7 @@ let isTwoAddress = 0 in { def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}">; def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), - "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", []>; def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2), @@ -1178,7 +1186,7 @@ let isTwoAddress = 0 in { def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), "sbb{b} {$src2, $dst|$dst, $src2}">; def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; + "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), "sbb{l} {$src2, $dst|$dst, $src2}">; @@ -1206,7 +1214,8 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), // Suprisingly enough, these are not two address instructions! def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 (ops R16:$dst, R16:$src1, i16imm:$src2), - "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, + "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", + [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize; def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 (ops R32:$dst, R32:$src1, i32imm:$src2), @@ -1221,7 +1230,7 @@ def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 (ops R32:$dst, i16mem:$src1, i16imm:$src2), - "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; + "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize; def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 (ops R32:$dst, i32mem:$src1, i32imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", []>; @@ -1261,7 +1270,7 @@ def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 "test{b} {$src2, $src1|$src1, $src2}">; def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 (ops R16:$src1, i16imm:$src2), - "test{w} {$src2, $src1|$src1, $src2}">, OpSize; + "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 (ops R32:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", []>; @@ -1270,7 +1279,7 @@ def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 "test{b} {$src2, $src1|$src1, $src2}">; def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 (ops i16mem:$src1, i16imm:$src2), - "test{w} {$src2, $src1|$src1, $src2}">, OpSize; + "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 (ops i32mem:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", []>; @@ -1371,7 +1380,7 @@ def CMP8ri : Ii8<0x80, MRM7r, "cmp{b} {$src2, $src1|$src1, $src2}">; def CMP16ri : Ii16<0x81, MRM7r, (ops R16:$src1, i16imm:$src2), - "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; + "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def CMP32ri : Ii32<0x81, MRM7r, (ops R32:$src1, i32imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", []>; @@ -1380,7 +1389,7 @@ def CMP8mi : Ii8 <0x80, MRM7m, "cmp{b} {$src2, $src1|$src1, $src2}">; def CMP16mi : Ii16<0x81, MRM7m, (ops i16mem:$src1, i16imm:$src2), - "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; + "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def CMP32mi : Ii32<0x81, MRM7m, (ops i32mem:$src1, i32imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", []>;