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ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocation

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Differential Revision: http://reviews.llvm.org/D15526


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270048 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2016-05-19 12:20:40 +00:00
parent e4c02144d1
commit 785d7f7fbf
7 changed files with 42 additions and 4 deletions
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2
include/llvm/Support/ELFRelocs/Mips.def
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@ -108,7 +108,7 @@ ELF_RELOC(R_MICROMIPS_TLS_TPREL_HI16, 169)
ELF_RELOC(R_MICROMIPS_TLS_TPREL_LO16, 170) ELF_RELOC(R_MICROMIPS_TLS_TPREL_LO16, 170)
ELF_RELOC(R_MICROMIPS_GPREL7_S2, 172) ELF_RELOC(R_MICROMIPS_GPREL7_S2, 172)
ELF_RELOC(R_MICROMIPS_PC23_S2, 173) ELF_RELOC(R_MICROMIPS_PC23_S2, 173)
ELF_RELOC(R_MICROMIPS_PC21_S2, 174) ELF_RELOC(R_MICROMIPS_PC21_S1, 174)
ELF_RELOC(R_MICROMIPS_PC26_S1, 175) ELF_RELOC(R_MICROMIPS_PC26_S1, 175)
ELF_RELOC(R_MICROMIPS_PC18_S3, 176) ELF_RELOC(R_MICROMIPS_PC18_S3, 176)
ELF_RELOC(R_MICROMIPS_PC19_S2, 177) ELF_RELOC(R_MICROMIPS_PC19_S2, 177)

12
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
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@ -189,7 +189,15 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
return 0; return 0;
} }
break; break;
case Mips::fixup_MICROMIPS_PC21_S1:
// Forcing a signed division because Value can be negative.
Value = (int64_t)Value / 2;
// We now check if Value can be encoded as a 21-bit signed immediate.
if (!isInt<21>(Value) && Ctx) {
Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
return 0;
}
break;
} }
return Value; return Value;
@ -343,6 +351,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_CALL16", 0, 16, 0 }, { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
@ -411,6 +420,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_CALL16", 16, 16, 0 }, { "fixup_MICROMIPS_CALL16", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },

4
lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
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@ -247,6 +247,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_MICROMIPS_PC19_S2; return ELF::R_MICROMIPS_PC19_S2;
case Mips::fixup_MICROMIPS_PC18_S3: case Mips::fixup_MICROMIPS_PC18_S3:
return ELF::R_MICROMIPS_PC18_S3; return ELF::R_MICROMIPS_PC18_S3;
case Mips::fixup_MICROMIPS_PC21_S1:
return ELF::R_MICROMIPS_PC21_S1;
case Mips::fixup_MIPS_PC19_S2: case Mips::fixup_MIPS_PC19_S2:
return ELF::R_MIPS_PC19_S2; return ELF::R_MIPS_PC19_S2;
case Mips::fixup_MIPS_PC18_S3: case Mips::fixup_MIPS_PC18_S3:
@ -608,7 +610,7 @@ bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
case ELF::R_MICROMIPS_TLS_TPREL_LO16: case ELF::R_MICROMIPS_TLS_TPREL_LO16:
case ELF::R_MICROMIPS_GPREL7_S2: case ELF::R_MICROMIPS_GPREL7_S2:
case ELF::R_MICROMIPS_PC23_S2: case ELF::R_MICROMIPS_PC23_S2:
case ELF::R_MICROMIPS_PC21_S2: case ELF::R_MICROMIPS_PC21_S1:
case ELF::R_MICROMIPS_PC26_S1: case ELF::R_MICROMIPS_PC26_S1:
case ELF::R_MICROMIPS_PC18_S3: case ELF::R_MICROMIPS_PC18_S3:
case ELF::R_MICROMIPS_PC19_S2: case ELF::R_MICROMIPS_PC19_S2:

3
lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
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@ -176,6 +176,9 @@ namespace Mips {
// resulting in - R_MICROMIPS_PC18_S3 // resulting in - R_MICROMIPS_PC18_S3
fixup_MICROMIPS_PC18_S3, fixup_MICROMIPS_PC18_S3,
// resulting in - R_MICROMIPS_PC21_S1
fixup_MICROMIPS_PC21_S1,
// resulting in - R_MICROMIPS_CALL16 // resulting in - R_MICROMIPS_CALL16
fixup_MICROMIPS_CALL16, fixup_MICROMIPS_CALL16,

5
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -384,7 +384,10 @@ getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
assert(MO.isExpr() && assert(MO.isExpr() &&
"getBranchTarget21OpValueMM expects only expressions or immediates"); "getBranchTarget21OpValueMM expects only expressions or immediates");
// TODO: Push fixup. const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
Fixups.push_back(MCFixup::create(0, FixupExpression,
MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
return 0; return 0;
} }

10
test/MC/Mips/micromips32r6/relocations.s
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@ -17,6 +17,12 @@
# CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
# CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -25,9 +31,13 @@
# CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x10 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
balc bar balc bar
bc bar bc bar
addiupc $2,bar addiupc $2,bar
lwpc $2,bar lwpc $2,bar
beqzc $3, bar
bnezc $3, bar

10
test/MC/Mips/micromips64r6/relocations.s
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@ -20,6 +20,12 @@
# CHECK-FIXUP: ldpc $2, bar # encoding: [0x78,0b010110AA,A,A] # CHECK-FIXUP: ldpc $2, bar # encoding: [0x78,0b010110AA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC18_S3 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC18_S3
# CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
# CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -29,6 +35,8 @@
# CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x10 R_MICROMIPS_PC18_S3 bar 0x0 # CHECK-ELF: 0x10 R_MICROMIPS_PC18_S3 bar 0x0
# CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
balc bar balc bar
@ -36,3 +44,5 @@
addiupc $2,bar addiupc $2,bar
lwpc $2,bar lwpc $2,bar
ldpc $2, bar ldpc $2, bar
beqzc $3, bar
bnezc $3, bar