From 78eedb15c90eb2cff925f51784a02cfb5cb93882 Mon Sep 17 00:00:00 2001 From: Kevin Qin Date: Fri, 25 Apr 2014 09:25:42 +0000 Subject: [PATCH] [ARM64] Support crc predicate on ARM64. According to the specification, CRC is an optional extension of the architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207214 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64.td | 14 +++++++++++--- lib/Target/ARM64/ARM64InstrFormats.td | 1 + lib/Target/ARM64/ARM64InstrInfo.td | 4 +++- lib/Target/ARM64/ARM64Subtarget.cpp | 2 +- lib/Target/ARM64/ARM64Subtarget.h | 2 ++ test/CodeGen/ARM64/crc32.ll | 2 +- test/MC/ARM64/basic-a64-instructions.s | 2 +- test/MC/ARM64/diagno-predicate.s | 7 ++++++- test/MC/Disassembler/ARM64/crc32.txt | 2 +- 9 files changed, 27 insertions(+), 9 deletions(-) diff --git a/lib/Target/ARM64/ARM64.td b/lib/Target/ARM64/ARM64.td index 69a126ce6a8..653f1574158 100644 --- a/lib/Target/ARM64/ARM64.td +++ b/lib/Target/ARM64/ARM64.td @@ -29,6 +29,9 @@ def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable cryptographic instructions">; +def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", + "Enable ARMv8 CRC-32 checksum instructions">; + /// Cyclone has register move instructions which are "free". def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", "Has zereo-cycle register moves">; @@ -63,22 +66,27 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [FeatureFPARMv8, FeatureNEON, - FeatureCrypto]>; + FeatureCrypto, + FeatureCRC]>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", [FeatureFPARMv8, FeatureNEON, - FeatureCrypto]>; + FeatureCrypto, + FeatureCRC]>; def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", "Cyclone", [FeatureFPARMv8, FeatureNEON, FeatureCrypto, + FeatureCRC, FeatureZCRegMove, FeatureZCZeroing]>; -def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, FeatureNEON]>; +def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, + FeatureNEON, + FeatureCRC]>; def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>; diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index 94fc2e0ab9f..2db7449d6aa 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -1243,6 +1243,7 @@ class BaseCRC32 sz, bit C, RegisterClass StreamReg, let Inst{11-10} = sz; let Inst{9-5} = Rn; let Inst{4-0} = Rd; + let Predicates = [HasCRC]; } //--- diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td index e4b47d7355d..ddcedee04c3 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.td +++ b/lib/Target/ARM64/ARM64InstrInfo.td @@ -18,8 +18,10 @@ def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "neon">; -def HasCrypto : Predicate<"Subtarget->hasCrypto()">, +def HasCrypto : Predicate<"Subtarget->hasCrypto()">, AssemblerPredicate<"FeatureCrypto", "crypto">; +def HasCRC : Predicate<"Subtarget->hasCRC()">, + AssemblerPredicate<"FeatureCRC", "crc">; //===----------------------------------------------------------------------===// // ARM64-specific DAG Nodes. diff --git a/lib/Target/ARM64/ARM64Subtarget.cpp b/lib/Target/ARM64/ARM64Subtarget.cpp index abe8e054ddf..e7cafbb3047 100644 --- a/lib/Target/ARM64/ARM64Subtarget.cpp +++ b/lib/Target/ARM64/ARM64Subtarget.cpp @@ -29,7 +29,7 @@ using namespace llvm; ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool LittleEndian) : ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), - HasFPARMv8(false), HasNEON(false), HasCrypto(false), + HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), CPUString(CPU), TargetTriple(TT), IsLittleEndian(LittleEndian) { // Determine default and user-specified characteristics diff --git a/lib/Target/ARM64/ARM64Subtarget.h b/lib/Target/ARM64/ARM64Subtarget.h index 1977e0bf05a..031068c4b86 100644 --- a/lib/Target/ARM64/ARM64Subtarget.h +++ b/lib/Target/ARM64/ARM64Subtarget.h @@ -35,6 +35,7 @@ protected: bool HasFPARMv8; bool HasNEON; bool HasCrypto; + bool HasCRC; // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove; @@ -66,6 +67,7 @@ public: bool hasFPARMv8() const { return HasFPARMv8; } bool hasNEON() const { return HasNEON; } bool hasCrypto() const { return HasCrypto; } + bool hasCRC() const { return HasCRC; } bool isLittleEndian() const { return IsLittleEndian; } diff --git a/test/CodeGen/ARM64/crc32.ll b/test/CodeGen/ARM64/crc32.ll index 609eb44122b..5d759dcce71 100644 --- a/test/CodeGen/ARM64/crc32.ll +++ b/test/CodeGen/ARM64/crc32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm64 -o - %s | FileCheck %s +; RUN: llc -march=arm64 -mattr=+crc -o - %s | FileCheck %s define i32 @test_crc32b(i32 %cur, i8 %next) { ; CHECK-LABEL: test_crc32b: diff --git a/test/MC/ARM64/basic-a64-instructions.s b/test/MC/ARM64/basic-a64-instructions.s index 99b438d64ba..2f58eadfc84 100644 --- a/test/MC/ARM64/basic-a64-instructions.s +++ b/test/MC/ARM64/basic-a64-instructions.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple arm64 -mattr=+crc -show-encoding < %s | FileCheck %s crc32b w5, w7, w20 crc32h w28, wzr, w30 diff --git a/test/MC/ARM64/diagno-predicate.s b/test/MC/ARM64/diagno-predicate.s index 399a85c631c..3b757e836d3 100644 --- a/test/MC/ARM64/diagno-predicate.s +++ b/test/MC/ARM64/diagno-predicate.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8 < %s 2> %t +// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8,-crc < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s @@ -15,5 +15,10 @@ pmull v0.1q, v1.1d, v2.1d // CHECK-ERROR: error: instruction requires: crypto // CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d +// CHECK-ERROR-NEXT: ^ + + crc32b w5, w7, w20 +// CHECK-ERROR: error: instruction requires: crc +// CHECK-ERROR-NEXT: crc32b w5, w7, w20 // CHECK-ERROR-NEXT: ^ diff --git a/test/MC/Disassembler/ARM64/crc32.txt b/test/MC/Disassembler/ARM64/crc32.txt index ef0a26e5629..51717ee2862 100644 --- a/test/MC/Disassembler/ARM64/crc32.txt +++ b/test/MC/Disassembler/ARM64/crc32.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=arm64 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s # CHECK: crc32b w5, w7, w20 # CHECK: crc32h w28, wzr, w30