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[mips] Make mips64 the default CPU for the mips64 architecture

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Summary:
This is consistent with the integrated assembler.
All mips64 codegen tests previously passed -mcpu. Removed -mcpu from
blez_bgez.ll and const-mult.ll to cover the default case.

Ideally, the two implementations of selectMipsCPU() will be merged but it's
proven difficult to find a home for the function that doesn't cause link errors.
For now, we'll hoist the common functionality into a function and mark it with
FIXME's.

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-02-20 13:13:33 +00:00
parent b584e193b5
commit 7934a2a9f1
4 changed files with 32 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -39,6 +39,20 @@
using namespace llvm;
/// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsSubtarget.cpp
static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
if (CPU.empty()) {
Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::mips ||
TheTriple.getArch() == Triple::mipsel)
CPU = "mips32";
else
CPU = "mips64";
}
return CPU;
}
static MCInstrInfo *createMipsMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMipsMCInstrInfo(X);
@ -53,15 +67,7 @@ static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
if (CPU.empty()) {
Triple TheTriple(TT);
// FIXME: CodeGen picks mips32 in both cases.
if (TheTriple.getArch() == Triple::mips ||
TheTriple.getArch() == Triple::mipsel)
CPU = "mips32";
else
CPU = "mips64";
}
CPU = selectMipsCPU(TT, CPU);
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X;

17
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -59,6 +59,20 @@ Mips16ConstantIslands(
cl::desc("MIPS: mips16 constant islands enable."),
cl::init(true));
/// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
if (CPU.empty()) {
Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::mips ||
TheTriple.getArch() == Triple::mipsel)
CPU = "mips32";
else
CPU = "mips64";
}
return CPU;
}
void MipsSubtarget::anchor() { }
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
@ -75,8 +89,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT)
{
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "mips32";
CPUName = selectMipsCPU(TT, CPUName);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);

2
test/CodeGen/Mips/blez_bgez.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
; RUN: llc -march=mips64el < %s | FileCheck %s
; CHECK-LABEL: test_blez:
; CHECK: blez ${{[0-9]+}}, $BB

2
test/CodeGen/Mips/const-mult.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64
; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64
; CHECK-LABEL: mul5_32:
; CHECK: sll $[[R0:[0-9]+]], $4, 2