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Switch Alpha over to the new call lowering style. New code mostly

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copied from the SystemZ target.  I don't think this causes any 
significant changes to the output (I compared the assembly, and the 
results appeared to be essentially unchanged), although I don't actually 
have an Alpha to test on.

I would appreciate if anyone with the appropriate hardware could test 
this. I'm not sure if that includes anyone subscribed to llvm-commits, 
though.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2009-07-19 01:11:32 +00:00
parent 10b547c638
commit 796492dc4b
5 changed files with 220 additions and 159 deletions
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6
lib/Target/Alpha/Alpha.td
View File

@ -29,6 +29,12 @@ def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
include "AlphaRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Calling Convention Description
//===----------------------------------------------------------------------===//
include "AlphaCallingConv.td"
//===----------------------------------------------------------------------===//
// Schedule Description
//===----------------------------------------------------------------------===//

37
lib/Target/Alpha/AlphaCallingConv.td Normal file
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@ -0,0 +1,37 @@
//===- AlphaCallingConv.td - Calling Conventions for Alpha -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// This describes the calling conventions for Alpha architecture.
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Alpha Return Value Calling Convention
//===----------------------------------------------------------------------===//
def RetCC_Alpha : CallingConv<[
// i64 is returned in register R0
CCIfType<[i64], CCAssignToReg<[R0]>>,
// f32 / f64 are returned in F0/F1
CCIfType<[f32, f64], CCAssignToReg<[F0, F1]>>
]>;
//===----------------------------------------------------------------------===//
// Alpha Argument Calling Conventions
//===----------------------------------------------------------------------===//
def CC_Alpha : CallingConv<[
// The first 6 arguments are passed in registers, whether integer or
// floating-point
CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
[F16, F17, F18, F19, F20, F21]>>,
CCIfType<[f32, f64], CCAssignToRegWithShadow<[F16, F17, F18, F19, F20, F21],
[R16, R17, R18, R19, R20, R21]>>,
// Stack slots are 8 bytes in size and 8-byte aligned.
CCIfType<[i64, f32, f64], CCAssignToStack<8, 8>>
]>;

75
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -446,55 +446,9 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
SDNode *N = Op.getNode();
SDValue Chain = N->getOperand(0);
SDValue Addr = N->getOperand(1);
SDValue InFlag(0,0); // Null incoming flag value.
SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
DebugLoc dl = N->getDebugLoc();
std::vector<SDValue> CallOperands;
std::vector<MVT> TypeOperands;
//grab the arguments
for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
TypeOperands.push_back(N->getOperand(i).getValueType());
CallOperands.push_back(N->getOperand(i));
}
int count = N->getNumOperands() - 2;
static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
Alpha::R19, Alpha::R20, Alpha::R21};
static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
Alpha::F19, Alpha::F20, Alpha::F21};
for (int i = 6; i < count; ++i) {
unsigned Opc = Alpha::WTF;
if (TypeOperands[i].isInteger()) {
Opc = Alpha::STQ;
} else if (TypeOperands[i] == MVT::f32) {
Opc = Alpha::STS;
} else if (TypeOperands[i] == MVT::f64) {
Opc = Alpha::STT;
} else
llvm_unreachable("Unknown operand");
SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
Chain };
Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0);
}
for (int i = 0; i < std::min(6, count); ++i) {
if (TypeOperands[i].isInteger()) {
Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i],
CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i],
CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else
llvm_unreachable("Unknown operand");
}
// Finally, once everything is in registers to pass to the call, emit the
// call itself.
if (Addr.getOpcode() == AlphaISD::GPRelLo) {
SDValue GOT = SDValue(getGlobalBaseReg(), 0);
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
@ -510,31 +464,8 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
}
InFlag = Chain.getValue(1);
std::vector<SDValue> CallResults;
switch (N->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:
Chain = CurDAG->getCopyFromReg(Chain, dl,
Alpha::R0, MVT::i64, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
case MVT::f32:
Chain = CurDAG->getCopyFromReg(Chain, dl,
Alpha::F0, MVT::f32, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
case MVT::f64:
Chain = CurDAG->getCopyFromReg(Chain, dl,
Alpha::F0, MVT::f64, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
}
CallResults.push_back(Chain);
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
ReplaceUses(Op.getValue(i), CallResults[i]);
ReplaceUses(Op.getValue(0), Chain);
ReplaceUses(Op.getValue(1), InFlag);
}

251
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -13,12 +13,14 @@
#include "AlphaISelLowering.h"
#include "AlphaTargetMachine.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/Module.h"
@ -223,6 +225,174 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
// //#define GP $29
// //#define SP $30
#include "AlphaGenCallingConv.inc"
SDValue AlphaTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
SDValue Chain = TheCall->getChain();
SDValue Callee = TheCall->getCallee();
bool isVarArg = TheCall->isVarArg();
DebugLoc dl = Op.getDebugLoc();
MachineFunction &MF = DAG.getMachineFunction();
unsigned CC = MF.getFunction()->getCallingConv();
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeCallOperands(TheCall, CC_Alpha);
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
getPointerTy(), true));
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
SmallVector<SDValue, 12> MemOpChains;
SDValue StackPtr;
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
// Arguments start after the 5 first operands of ISD::CALL
SDValue Arg = TheCall->getArg(i);
// Promote the value if needed.
switch (VA.getLocInfo()) {
default: assert(0 && "Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::ZExt:
Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::AExt:
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
break;
}
// Arguments that can be passed on register must be kept at RegsToPass
// vector
if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} else {
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset()));
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
PseudoSourceValue::getStack(), 0));
}
}
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
// flag operands which copy the outgoing args into registers. The InFlag in
// necessary since all emited instructions must be stuck together.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
// Add argument registers to the end of the list so that they are
// known live into the call.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
if (InFlag.getNode())
Ops.push_back(InFlag);
Chain = DAG.getNode(AlphaISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, getPointerTy(), true),
DAG.getConstant(0, getPointerTy(), true),
InFlag);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
// return.
return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
Op.getResNo());
}
/// LowerCallResult - Lower the result values of an ISD::CALL into the
/// appropriate copies out of appropriate physical registers. This assumes that
/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
/// being lowered. Returns a SDNode with the same number of values as the
/// ISD::CALL.
SDNode*
AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallSDNode *TheCall,
unsigned CallingConv,
SelectionDAG &DAG) {
bool isVarArg = TheCall->isVarArg();
DebugLoc dl = TheCall->getDebugLoc();
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs,
DAG.getContext());
CCInfo.AnalyzeCallResult(TheCall, RetCC_Alpha);
SmallVector<SDValue, 8> ResultVals;
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
VA.getLocVT(), InFlag).getValue(1);
SDValue RetValue = Chain.getValue(0);
InFlag = Chain.getValue(2);
// If this is an 8/16/32-bit value, it is really passed promoted to 64
// bits. Insert an assert[sz]ext to capture this, then truncate to the
// right size.
if (VA.getLocInfo() == CCValAssign::SExt)
RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::ZExt)
RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
DAG.getValueType(VA.getValVT()));
if (VA.getLocInfo() != CCValAssign::Full)
RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
ResultVals.push_back(RetValue);
}
ResultVals.push_back(Chain);
// Merge everything together with a MERGE_VALUES node.
return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
&ResultVals[0], ResultVals.size()).getNode();
}
static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsBase,
int &VarArgsOffset) {
@ -365,85 +535,6 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
MVT::Other, Copy, Copy.getValue(1));
}
std::pair<SDValue, SDValue>
AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned NumFixedArgs,
unsigned CallingConv,
bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG,
DebugLoc dl) {
int NumBytes = 0;
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
std::vector<SDValue> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty).getSimpleVT()) {
default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
// Promote the integer to 64 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
if (Args[i].isSExt)
Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl,
MVT::i64, Args[i].Node);
else if (Args[i].isZExt)
Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl,
MVT::i64, Args[i].Node);
else
Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node);
break;
case MVT::i64:
case MVT::f64:
case MVT::f32:
break;
}
args_to_use.push_back(Args[i].Node);
}
std::vector<MVT> RetVals;
MVT RetTyVT = getValueType(RetTy);
MVT ActualRetTyVT = RetTyVT;
if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
ActualRetTyVT = MVT::i64;
if (RetTyVT != MVT::isVoid)
RetVals.push_back(ActualRetTyVT);
RetVals.push_back(MVT::Other);
std::vector<SDValue> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl,
RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
DAG.getIntPtrConstant(0, true), SDValue());
SDValue RetVal = TheCall;
if (RetTyVT != ActualRetTyVT) {
ISD::NodeType AssertKind = ISD::DELETED_NODE;
if (RetSExt)
AssertKind = ISD::AssertSext;
else if (RetZExt)
AssertKind = ISD::AssertZext;
if (AssertKind != ISD::DELETED_NODE)
RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal,
DAG.getValueType(RetTyVT));
RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
}
return std::make_pair(RetVal, Chain);
}
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
SDValue &DataPtr, SelectionDAG &DAG) {
Chain = N->getOperand(0);
@ -482,7 +573,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
VarArgsBase,
VarArgsOffset);
case ISD::CALL: return LowerCALL(Op, DAG);
case ISD::RET: return LowerRET(Op,DAG);
case ISD::JumpTable: return LowerJumpTable(Op, DAG);

10
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -82,13 +82,9 @@ namespace llvm {
// Friendly names for dumps
const char *getTargetNodeName(unsigned Opcode) const;
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, bool isInreg, unsigned NumFixedArgs, unsigned CC,
bool isTailCall, SDValue Callee, ArgListTy &Args,
SelectionDAG &DAG, DebugLoc dl);
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG);
ConstraintType getConstraintType(const std::string &Constraint) const;