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[ARM] Don't pessimize i32 vselect.

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The underlying issues surrounding codegen for 32-bit vselects have been resolved. The pessimistic costs for 64-bit vselects remain due to the bad
scalarization that is still happening there.

I tested this on A57 in T32, A32 and A64 modes. I saw no regressions, and some improvements.

From my benchmarks, I saw these improvements in A57 (T32)
spec.cpu2000.ref.177_mesa 5.95%
lnt.SingleSource/Benchmarks/Shootout/strcat 12.93%
lnt.MultiSource/Benchmarks/MiBench/telecomm-CRC32/telecomm-CRC32 11.89%

I also measured A57 A32, A53 T32 and A9 T32 and found no performance regressions. I see much bigger wins in third-party benchmarks with this change

Differential Revision: http://reviews.llvm.org/D14743



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253349 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Charlie Turner 2015-11-17 17:25:15 +00:00
parent 7271f32728
commit 7a016a152d
3 changed files with 9 additions and 11 deletions
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3
lib/Target/ARM/ARMTargetTransformInfo.cpp
View File

@ -274,9 +274,6 @@ int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
// Lowering of some vector selects is currently far from perfect.
static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = {
{ ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
{ ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
{ ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
{ ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
{ ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
{ ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }

6
test/Analysis/CostModel/ARM/select.ll
View File

@ -34,16 +34,16 @@ define void @casts() {
%v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef
; CHECK: cost of 1 {{.*}} select
%v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef
; CHECK: cost of 40 {{.*}} select
; CHECK: cost of 2 {{.*}} select
%v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef
; CHECK: cost of 1 {{.*}} select
%v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef
; CHECK: cost of 1 {{.*}} select
%v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef
; CHECK: cost of 41 {{.*}} select
; CHECK: cost of 2 {{.*}} select
%v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef
; CHECK: cost of 82 {{.*}} select
; CHECK: cost of 4 {{.*}} select
%v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef
; CHECK: cost of 1 {{.*}} select

11
test/CodeGen/ARM/vselect_imax.ll
View File

@ -10,8 +10,6 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
ret void
}
; We adjusted the cost model of the following selects. When we improve code
; lowering we also need to adjust the cost.
%T0_10 = type <16 x i16>
%T1_10 = type <16 x i1>
; CHECK-LABEL: func_blend10:
@ -23,7 +21,7 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
; CHECK: vmin.s16
; CHECK: vmin.s16
; COST: func_blend10
; COST: cost of 40 {{.*}} select
; COST: cost of 2 {{.*}} select
%r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1
store %T0_10 %r, %T0_10* %storeaddr
ret void
@ -39,7 +37,7 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
; CHECK: vmin.s32
; CHECK: vmin.s32
; COST: func_blend14
; COST: cost of 41 {{.*}} select
; COST: cost of 2 {{.*}} select
%r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1
store %T0_14 %r, %T0_14* %storeaddr
ret void
@ -55,11 +53,14 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
%v1 = load %T0_15, %T0_15* %loadaddr2
%c = icmp slt %T0_15 %v0, %v1
; COST: func_blend15
; COST: cost of 82 {{.*}} select
; COST: cost of 4 {{.*}} select
%r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1
store %T0_15 %r, %T0_15* %storeaddr
ret void
}
; We adjusted the cost model of the following selects. When we improve code
; lowering we also need to adjust the cost.
%T0_18 = type <4 x i64>
%T1_18 = type <4 x i1>
; CHECK-LABEL: func_blend18: