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[PPC] Fix atomics lowering in DAG lowering.
I forgot to forward the chain, causing some missing instruction dependencies. The test crashes the compiler without this patch. Inspired by the test case, D33519 also tries to remove the extra sync. Differential Revision: https://reviews.llvm.org/D33573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303931 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8296,10 +8296,12 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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SDLoc DL(Op);
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switch (cast<ConstantSDNode>(Op.getOperand(ArgStart))->getZExtValue()) {
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case Intrinsic::ppc_cfence: {
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assert(ArgStart == 1);
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assert(Subtarget.isPPC64() && "Only 64-bit is supported for now.");
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return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
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DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
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Op.getOperand(ArgStart + 1))),
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Op.getOperand(ArgStart + 1)),
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Op.getOperand(0)),
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0);
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}
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default:
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23
test/CodeGen/PowerPC/atomics-constant.ll
Normal file
23
test/CodeGen/PowerPC/atomics-constant.ll
Normal file
@ -0,0 +1,23 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "powerpc64le-unknown-linux-gnu"
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@a = constant i64 zeroinitializer
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define i64 @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: cmpw 7, 4, 4
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: bne- 7, .+4
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; CHECK-NEXT: isync
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: blr
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entry:
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%value = load atomic i64, i64* @a acquire, align 8
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ret i64 %value
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}
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