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clean this function up some

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2006-01-01 22:13:54 +00:00
parent b0bff9eefe
commit 7a832da304
1 changed files with 26 additions and 37 deletions
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63
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@ -126,43 +126,32 @@ AlphaRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned OpNum, unsigned OpNum,
int FrameIndex) const { int FrameIndex) const {
// Make sure this is a reg-reg copy. // Make sure this is a reg-reg copy.
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
if ((Opc == Alpha::BIS && switch(Opc) {
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { default:
if (OpNum == 0) { // move -> store break;
unsigned InReg = MI->getOperand(1).getReg(); case Alpha::BIS:
return BuildMI(Alpha::STQ, 3).addReg(InReg).addFrameIndex(FrameIndex) case Alpha::CPYSS:
.addReg(Alpha::F31); case Alpha::CPYST:
} else { // load -> move if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
unsigned OutReg = MI->getOperand(0).getReg(); if (OpNum == 0) { // move -> store
return BuildMI(Alpha::LDQ, 2, OutReg).addFrameIndex(FrameIndex) unsigned InReg = MI->getOperand(1).getReg();
.addReg(Alpha::F31); Opc = (Opc == Alpha::BIS) ? Alpha::STQ :
} ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
} else if ((Opc == Alpha::CPYSS && return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { .addReg(Alpha::F31);
if (OpNum == 0) { // move -> store } else { // load -> move
unsigned InReg = MI->getOperand(1).getReg(); unsigned OutReg = MI->getOperand(0).getReg();
return BuildMI(Alpha::STS, 3).addReg(InReg).addFrameIndex(FrameIndex) Opc = (Opc == Alpha::BIS) ? Alpha::LDQ :
.addReg(Alpha::F31); ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
} else { // load -> move return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
unsigned OutReg = MI->getOperand(0).getReg(); .addReg(Alpha::F31);
return BuildMI(Alpha::LDS, 2, OutReg).addFrameIndex(FrameIndex) }
.addReg(Alpha::F31); }
} break;
} else if ((Opc == Alpha::CPYST && }
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return BuildMI(Alpha::STT, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
return BuildMI(Alpha::LDT, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
}
return 0; return 0;
} }