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AArch64 & ARM: remove undefined behaviour from some tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209880 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-30 08:59:55 +00:00
parent fd481d05be
commit 7be505ae88
13 changed files with 66 additions and 62 deletions
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6
test/CodeGen/AArch64/arm64-2012-05-09-LOADgot-bug.ll
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@ -2,14 +2,14 @@
; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic < %s | FileCheck %s --check-prefix=CHECK-LINUX
; <rdar://problem/11392109>
define hidden void @t() optsize ssp {
define hidden void @t(i64* %addr) optsize ssp {
entry:
store i64 zext (i32 ptrtoint (i64 (i32)* @x to i32) to i64), i64* undef, align 8
store i64 zext (i32 ptrtoint (i64 (i32)* @x to i32) to i64), i64* %addr, align 8
; CHECK: adrp x{{[0-9]+}}, _x@GOTPAGE
; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}, _x@GOTPAGEOFF]
; CHECK-NEXT: and x{{[0-9]+}}, x{{[0-9]+}}, #0xffffffff
; CHECK-NEXT: str x{{[0-9]+}}, [x{{[0-9]+}}]
unreachable
ret void
}
declare i64 @x(i32) optsize

8
test/CodeGen/AArch64/arm64-ands-bad-peephole.ll
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@ -8,18 +8,18 @@ target triple = "arm64-apple-ios"
; CHECK-LABEL: tst1:
; CHECK: add [[REG:w[0-9]+]], w{{[0-9]+}}, #1
; CHECK: tst [[REG]], #0x1
define void @tst1() {
define void @tst1(i1 %tst, i32 %true) {
entry:
br i1 undef, label %for.end, label %for.body
br i1 %tst, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry
%result.09 = phi i32 [ %add2.result.0, %for.body ], [ 1, %entry ]
%i.08 = phi i32 [ %inc, %for.body ], [ 2, %entry ]
%and = and i32 %i.08, 1
%cmp1 = icmp eq i32 %and, 0
%add2.result.0 = select i1 %cmp1, i32 undef, i32 %result.09
%add2.result.0 = select i1 %cmp1, i32 %true, i32 %result.09
%inc = add nsw i32 %i.08, 1
%cmp = icmp slt i32 %i.08, undef
%cmp = icmp slt i32 %i.08, %true
br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
for.cond.for.end_crit_edge: ; preds = %for.body

12
test/CodeGen/AArch64/arm64-convert-v2f64-v2i32.ll
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@ -4,10 +4,10 @@
; CHECK: fcvtzs.2d
; CHECK: xtn.2s
; CHECK: ret
define void @fptosi_1() nounwind noinline ssp {
define void @fptosi_1(<2 x double> %in, <2 x i32>* %addr) nounwind noinline ssp {
entry:
%0 = fptosi <2 x double> undef to <2 x i32>
store <2 x i32> %0, <2 x i32>* undef, align 8
%0 = fptosi <2 x double> %in to <2 x i32>
store <2 x i32> %0, <2 x i32>* %addr, align 8
ret void
}
@ -15,10 +15,10 @@ entry:
; CHECK: fcvtzu.2d
; CHECK: xtn.2s
; CHECK: ret
define void @fptoui_1() nounwind noinline ssp {
define void @fptoui_1(<2 x double> %in, <2 x i32>* %addr) nounwind noinline ssp {
entry:
%0 = fptoui <2 x double> undef to <2 x i32>
store <2 x i32> %0, <2 x i32>* undef, align 8
%0 = fptoui <2 x double> %in to <2 x i32>
store <2 x i32> %0, <2 x i32>* %addr, align 8
ret void
}

8
test/CodeGen/AArch64/arm64-convert-v2i32-v2f64.ll
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@ -20,10 +20,10 @@ define <2 x double> @f2(<2 x i32> %v) nounwind readnone {
; CHECK: autogen_SD19655
; CHECK: scvtf
; CHECK: ret
define void @autogen_SD19655() {
%T = load <2 x i64>* undef
%F = sitofp <2 x i64> undef to <2 x float>
store <2 x float> %F, <2 x float>* undef
define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
%T = load <2 x i64>* %addr
%F = sitofp <2 x i64> %T to <2 x float>
store <2 x float> %F, <2 x float>* %addrfloat
ret void
}

16
test/CodeGen/AArch64/arm64-dagcombiner-indexed-load.ll
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@ -13,12 +13,12 @@ target triple = "arm64-apple-ios"
; CHECK-LABEL: XX:
; CHECK: ldr
define void @XX(%class.A* %K) {
define i32 @XX(%class.A* %K, i1 %tst, i32* %addr, %class.C** %ppC, %class.C* %pC) {
entry:
br i1 undef, label %if.then, label %lor.rhs.i
br i1 %tst, label %if.then, label %lor.rhs.i
lor.rhs.i: ; preds = %entry
%tmp = load i32* undef, align 4
%tmp = load i32* %addr, align 4
%y.i.i.i = getelementptr inbounds %class.A* %K, i64 0, i32 1
%tmp1 = load i64* %y.i.i.i, align 8
%U.sroa.3.8.extract.trunc.i = trunc i64 %tmp1 to i32
@ -30,17 +30,17 @@ lor.rhs.i: ; preds = %entry
%add16.i = add nsw i32 %add12.i, %div15.i
%rem.i.i = srem i32 %add16.i, %tmp
%idxprom = sext i32 %rem.i.i to i64
%arrayidx = getelementptr inbounds %class.C** undef, i64 %idxprom
%tobool533 = icmp eq %class.C* undef, null
%arrayidx = getelementptr inbounds %class.C** %ppC, i64 %idxprom
%tobool533 = icmp eq %class.C* %pC, null
br i1 %tobool533, label %while.end, label %while.body
if.then: ; preds = %entry
unreachable
ret i32 42
while.body: ; preds = %lor.rhs.i
unreachable
ret i32 5
while.end: ; preds = %lor.rhs.i
%tmp3 = load %class.C** %arrayidx, align 8
unreachable
ret i32 50
}

12
test/CodeGen/AArch64/arm64-vcvt.ll
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@ -665,19 +665,19 @@ define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind {
;CHECK-LABEL: autogen_SD28458:
;CHECK: fcvt
;CHECK: ret
define void @autogen_SD28458() {
%Tr53 = fptrunc <8 x double> undef to <8 x float>
store <8 x float> %Tr53, <8 x float>* undef
define void @autogen_SD28458(<8 x double> %val.f64, <8 x float>* %addr.f32) {
%Tr53 = fptrunc <8 x double> %val.f64 to <8 x float>
store <8 x float> %Tr53, <8 x float>* %addr.f32
ret void
}
;CHECK-LABEL: autogen_SD19225:
;CHECK: fcvt
;CHECK: ret
define void @autogen_SD19225() {
%A = load <8 x float>* undef
define void @autogen_SD19225(<8 x double>* %addr.f64, <8 x float>* %addr.f32) {
%A = load <8 x float>* %addr.f32
%Tr53 = fpext <8 x float> %A to <8 x double>
store <8 x double> %Tr53, <8 x double>* undef
store <8 x double> %Tr53, <8 x double>* %addr.f64
ret void
}

18
test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
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@ -4,22 +4,26 @@
%struct.foo = type { i64, i64 }
define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
define zeroext i8 @t(%struct.foo* %this, i1 %tst) noreturn optsize {
entry:
; ARM-LABEL: t:
; ARM: str r2, [r1], r0
; ARM-DAG: mov r[[ADDR:[0-9]+]], #8
; ARM-DAG: mov [[VAL:r[0-9]+]], #0
; ARM: str [[VAL]], [r[[ADDR]]], r0
; THUMB-LABEL: t:
; THUMB-NOT: str r0, [r1], r0
; THUMB: str r1, [r0]
; THUMB-DAG: movs r[[ADDR:[0-9]+]], #8
; THUMB-DAG: movs [[VAL:r[0-9]+]], #0
; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}}
; THUMB: str [[VAL]], [r[[ADDR]]]
%0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
store i32 0, i32* inttoptr (i32 8 to i32*), align 8
br i1 undef, label %bb.nph96, label %bb3
br i1 %tst, label %bb.nph96, label %bb3
bb3: ; preds = %entry
%1 = load i64* %0, align 4 ; <i64> [#uses=0]
unreachable
ret i8 42
bb.nph96: ; preds = %entry
unreachable
ret i8 3
}

2
test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
View File

@ -11,7 +11,7 @@
define i32 @test(i32 %x) {
entry:
%0 = tail call signext i16 undef(i32* undef)
switch i32 undef, label %bb3 [
switch i32 %x, label %bb3 [
i32 0, label %bb4
i32 1, label %bb1
i32 2, label %bb2

18
test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
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@ -7,7 +7,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
target triple = "armv6-apple-darwin10"
define void @ptoa() nounwind {
define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind {
entry:
br i1 false, label %bb3, label %bb
@ -16,7 +16,7 @@ bb: ; preds = %entry
bb3: ; preds = %bb, %entry
%0 = call noalias i8* @malloc() nounwind
br i1 undef, label %bb46, label %bb8
br i1 %tst, label %bb46, label %bb8
bb8: ; preds = %bb3
%1 = getelementptr inbounds i8* %0, i32 0
@ -35,7 +35,7 @@ bb8: ; preds = %bb3
%7 = or i8 %6, 48
%8 = add i8 %6, 87
%iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8
store i8 %iftmp.5.0.1, i8* undef, align 1
store i8 %iftmp.5.0.1, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@ -49,7 +49,7 @@ bb8: ; preds = %bb3
%13 = or i8 %12, 48
%14 = add i8 %12, 87
%iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14
store i8 %iftmp.5.0.2, i8* undef, align 1
store i8 %iftmp.5.0.2, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@ -73,8 +73,8 @@ bb8: ; preds = %bb3
%21 = udiv i32 %2, 100000
%22 = urem i32 %21, 10
%23 = icmp ult i32 %22, 10
%iftmp.5.0.5 = select i1 %23, i8 0, i8 undef
store i8 %iftmp.5.0.5, i8* undef, align 1
%iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8
store i8 %iftmp.5.0.5, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@ -88,7 +88,7 @@ bb8: ; preds = %bb3
%28 = or i8 %27, 48
%29 = add i8 %27, 87
%iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29
store i8 %iftmp.5.0.6, i8* undef, align 1
store i8 %iftmp.5.0.6, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@ -102,7 +102,7 @@ bb8: ; preds = %bb3
%34 = or i8 %33, 48
%35 = add i8 %33, 87
%iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35
store i8 %iftmp.5.0.7, i8* undef, align 1
store i8 %iftmp.5.0.7, i8* %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
@ -117,7 +117,7 @@ bb8: ; preds = %bb3
%41 = add i8 %39, 87
%iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41
store i8 %iftmp.5.0.8, i8* null, align 1
unreachable
br label %bb46
bb46: ; preds = %bb3
ret void

6
test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
View File

@ -8,7 +8,7 @@
@oStruct = external global %struct.Outer, align 4
define void @main() nounwind {
define void @main(i8 %val8) nounwind {
; CHECK-LABEL: main:
; CHECK-NOT: ldrd
; CHECK: mul
@ -28,7 +28,7 @@ for.body: ; preds = %_Z14printIsNotZeroi
br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16
if.then.i16: ; preds = %_Z14printIsNotZeroi.exit
unreachable
ret void
_Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi.exit
br label %_Z14printIsNotZeroi.exit17.for.body_crit_edge
@ -36,7 +36,7 @@ _Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi
_Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17
%b.phi.trans.insert = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3
%tmp3.pre = load i8* %b.phi.trans.insert, align 1
%phitmp27 = icmp eq i8 undef, 0
%phitmp27 = icmp eq i8 %val8, 0
br label %for.body
for.end: ; preds = %_Z14printIsNotZeroi.exit17

12
test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
View File

@ -42,34 +42,34 @@ UnifiedReturnBlock:
ret i32 %tmp13
}
define hidden fastcc void @t3(i8** %retaddr) {
define hidden fastcc void @t3(i8** %retaddr, i1 %tst, i8* %p8) {
; CHECK-LABEL: t3:
; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen
bb:
store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr
br i1 undef, label %bb77, label %bb7.i
br i1 %tst, label %bb77, label %bb7.i
bb7.i: ; preds = %bb35
br label %bb2.i
KBBlockZero_return_1: ; preds = %KBBlockZero.exit
unreachable
ret void
KBBlockZero_return_0: ; preds = %KBBlockZero.exit
unreachable
ret void
bb77: ; preds = %bb26, %bb12, %bb
ret void
bb2.i: ; preds = %bb6.i350, %bb7.i
br i1 undef, label %bb6.i350, label %KBBlockZero.exit
br i1 %tst, label %bb6.i350, label %KBBlockZero.exit
bb6.i350: ; preds = %bb2.i
br label %bb2.i
KBBlockZero.exit: ; preds = %bb2.i
indirectbr i8* undef, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
indirectbr i8* %p8, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
}
@foo = global i32 ()* null

4
test/CodeGen/ARM/va_arg.ll
View File

@ -24,13 +24,13 @@ entry:
; CHECK-NOT: bfc
; CHECK: bx lr
define double @test2(i32 %a, i32 %b, ...) nounwind optsize {
define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
entry:
%ap = alloca i8*, align 4 ; <i8**> [#uses=3]
%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
call void @llvm.va_start(i8* %ap1)
%0 = va_arg i8** %ap, i32 ; <i32> [#uses=0]
store i32 %0, i32* undef
store i32 %0, i32* %b
%1 = va_arg i8** %ap, double ; <double> [#uses=1]
call void @llvm.va_end(i8* %ap1)
ret double %1

6
test/CodeGen/ARM/widen-vmovs.ll
View File

@ -17,7 +17,7 @@ target triple = "thumbv7-apple-ios"
; - Register liveness is verified.
; - The execution domain switch to vorr works across basic blocks.
define void @Mm() nounwind {
define void @Mm(i32 %in, float* %addr) nounwind {
entry:
br label %for.body4
@ -27,10 +27,10 @@ for.body4:
for.body.i:
%tmp3.i = phi float [ 1.000000e+10, %for.body4 ], [ %add.i, %for.body.i ]
%add.i = fadd float %tmp3.i, 1.000000e+10
%exitcond.i = icmp eq i32 undef, 41
%exitcond.i = icmp eq i32 %in, 41
br i1 %exitcond.i, label %rInnerproduct.exit, label %for.body.i
rInnerproduct.exit:
store float %add.i, float* undef, align 4
store float %add.i, float* %addr, align 4
br label %for.body4
}