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Oops. Didn't mean to check in a quick hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36227 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -34,18 +34,26 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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MRegisterInfo::~MRegisterInfo() {}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
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E = RC->allocation_order_end(MF); I != E; ++I)
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R.set(*I);
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}
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BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(NumRegs);
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for (MRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I) {
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const TargetRegisterClass *TRC = *I;
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if (RC && TRC != RC)
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continue;
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF),
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E = TRC->allocation_order_end(MF); I != E; ++I)
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Allocatable.set(*I);
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if (RC) {
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getAllocatableSetForRC(MF, RC, Allocatable);
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return Allocatable;
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}
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for (MRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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getAllocatableSetForRC(MF, *I, Allocatable);
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return Allocatable;
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}
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