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[X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
dd9c0f58f9
commit
7bef62dc08
@ -3946,126 +3946,94 @@ defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw,
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let ExeDomain = SSEPackedInt in {
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multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, OpndItins itins,
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PatFrag ld_frag, bit Is2Addr = 1> {
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ValueType ArgVT, SDNode OpNode, RegisterClass RC,
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X86MemOperand x86memop, OpndItins itins, PatFrag ld_frag,
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bit Is2Addr = 1> {
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def rr : PDI<opc, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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(outs RC:$dst), (ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))],
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[(set RC:$dst,
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(OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))],
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itins.rr>, Sched<[itins.Sched]>;
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def rm : PDI<opc, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode (ArgVT VR128:$src1),
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[(set RC:$dst,
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(OutVT (OpNode (ArgVT RC:$src1),
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(bitconvert (ld_frag addr:$src2)))))],
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itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, OpndItins itins> {
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def Yrr : PDI<opc, MRMSrcReg,
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(outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))],
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itins.rr>, Sched<[itins.Sched]>;
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def Yrm : PDI<opc, MRMSrcMem,
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(outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode (ArgVT VR256:$src1),
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(bitconvert (loadv4i64 addr:$src2)))))],
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itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, OpndItins itins,
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PatFrag ld_frag, bit Is2Addr = 1> {
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ValueType ArgVT, SDNode OpNode, RegisterClass RC,
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X86MemOperand x86memop, OpndItins itins, PatFrag ld_frag,
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bit Is2Addr = 1> {
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def rr : SS48I<opc, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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(outs RC:$dst), (ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))],
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[(set RC:$dst,
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(OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))],
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itins.rr>, Sched<[itins.Sched]>;
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def rm : SS48I<opc, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(OutVT (OpNode (ArgVT VR128:$src1),
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[(set RC:$dst,
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(OutVT (OpNode (ArgVT RC:$src1),
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(bitconvert (ld_frag addr:$src2)))))],
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itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
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ValueType ArgVT, SDNode OpNode, OpndItins itins> {
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def Yrr : SS48I<opc, MRMSrcReg,
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(outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))],
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itins.rr>, Sched<[itins.Sched]>;
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def Yrm : SS48I<opc, MRMSrcMem,
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(outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OutVT (OpNode (ArgVT VR256:$src1),
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(bitconvert (loadv4i64 addr:$src2)))))],
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itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
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defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
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SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
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defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
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SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
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defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss, VR128,
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i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
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defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss, VR128,
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i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
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defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
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SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
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defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
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SSE_PACK, loadv2i64, 0>, VEX_4V;
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defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus, VR128,
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i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V, VEX_WIG;
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defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus, VR128,
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i128mem, SSE_PACK, loadv2i64, 0>, VEX_4V;
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}
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let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
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defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss, SSE_PACK>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss, SSE_PACK>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPACKSSWBY : sse2_pack<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
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VR256, i256mem, SSE_PACK, loadv4i64, 0>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPACKSSDWY : sse2_pack<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
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VR256, i256mem, SSE_PACK, loadv4i64, 0>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus, SSE_PACK>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus, SSE_PACK>,
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VEX_4V, VEX_L;
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defm VPACKUSWBY : sse2_pack<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
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VR256,i256mem, SSE_PACK, loadv4i64, 0>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPACKUSDWY : sse4_pack<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
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VR256, i256mem, SSE_PACK, loadv4i64, 0>,
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VEX_4V, VEX_L;
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}
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let Constraints = "$src1 = $dst" in {
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defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss, SSE_PACK,
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memopv2i64>;
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defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss, SSE_PACK,
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memopv2i64>;
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defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss, VR128,
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i128mem, SSE_PACK, memopv2i64>;
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defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss, VR128,
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i128mem, SSE_PACK, memopv2i64>;
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defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus, SSE_PACK,
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memopv2i64>;
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defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus, VR128,
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i128mem, SSE_PACK, memopv2i64>;
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defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus, SSE_PACK,
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memopv2i64>;
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defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus, VR128,
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i128mem, SSE_PACK, memopv2i64>;
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}
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} // ExeDomain = SSEPackedInt
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