From 7c0d664c2118d1c5da50b137856d4a6b1c962ec3 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 2 Oct 2005 06:37:13 +0000 Subject: [PATCH] fix an f32/f64 type mismatch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index fdefef7c237..9bab6ed8be3 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -130,13 +130,17 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { default: assert(0 && "Wasn't expecting to be able to lower this!"); case ISD::FP_TO_SINT: { assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); + SDOperand Src = Op.getOperand(0); + if (Src.getValueType() == MVT::f32) + Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); + switch (Op.getValueType()) { default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); case MVT::i32: - Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0)); + Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); break; case MVT::i64: - Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0)); + Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); break; }