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Sink InstructionSelect() out of each target into SDISel, and rename it

Browse Source 
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-03-02 06:34:30 +00:00
parent 8d17882efa
commit 7c306da505
17 changed files with 114 additions and 430 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

91
include/llvm/CodeGen/DAGISelHeader.h
View File

@ -21,97 +21,6 @@
#ifndef LLVM_CODEGEN_DAGISEL_HEADER_H
#define LLVM_CODEGEN_DAGISEL_HEADER_H
/// ISelPosition - Node iterator marking the current position of
/// instruction selection as it procedes through the topologically-sorted
/// node list.
SelectionDAG::allnodes_iterator ISelPosition;
/// ISelUpdater - helper class to handle updates of the
/// instruciton selection graph.
class VISIBILITY_HIDDEN ISelUpdater : public SelectionDAG::DAGUpdateListener {
SelectionDAG::allnodes_iterator &ISelPosition;
public:
explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
: ISelPosition(isp) {}
/// NodeDeleted - Handle nodes deleted from the graph. If the
/// node being deleted is the current ISelPosition node, update
/// ISelPosition.
///
virtual void NodeDeleted(SDNode *N, SDNode *E) {
if (ISelPosition == SelectionDAG::allnodes_iterator(N))
++ISelPosition;
}
/// NodeUpdated - Ignore updates for now.
virtual void NodeUpdated(SDNode *N) {}
};
/// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T.
DISABLE_INLINE void ReplaceUses(SDValue F, SDValue T) {
ISelUpdater ISU(ISelPosition);
CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
}
/// ReplaceUses - replace all uses of the old nodes F with the use
/// of the new nodes T.
DISABLE_INLINE void ReplaceUses(const SDValue *F, const SDValue *T,
unsigned Num) {
ISelUpdater ISU(ISelPosition);
CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
}
/// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T.
DISABLE_INLINE void ReplaceUses(SDNode *F, SDNode *T) {
ISelUpdater ISU(ISelPosition);
CurDAG->ReplaceAllUsesWith(F, T, &ISU);
}
/// SelectRoot - Top level entry to DAG instruction selector.
/// Selects instructions starting at the root of the current DAG.
void SelectRoot(SelectionDAG &DAG) {
SelectRootInit();
// Create a dummy node (which is not added to allnodes), that adds
// a reference to the root node, preventing it from being deleted,
// and tracking any changes of the root.
HandleSDNode Dummy(CurDAG->getRoot());
ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
++ISelPosition;
// The AllNodes list is now topological-sorted. Visit the
// nodes by starting at the end of the list (the root of the
// graph) and preceding back toward the beginning (the entry
// node).
while (ISelPosition != CurDAG->allnodes_begin()) {
SDNode *Node = --ISelPosition;
// Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
// but there are currently some corner cases that it misses. Also, this
// makes it theoretically possible to disable the DAGCombiner.
if (Node->use_empty())
continue;
SDNode *ResNode = Select(Node);
// If node should not be replaced, continue with the next one.
if (ResNode == Node)
continue;
// Replace node.
if (ResNode)
ReplaceUses(Node, ResNode);
// If after the replacement this node is not used any more,
// remove this dead node.
if (Node->use_empty()) { // Don't delete EntryToken, etc.
ISelUpdater ISU(ISelPosition);
CurDAG->RemoveDeadNode(Node, &ISU);
}
}
CurDAG->setRoot(Dummy.getValue());
}
#endif /* LLVM_CODEGEN_DAGISEL_HEADER_H */

18
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -68,12 +68,18 @@ public:
unsigned MakeReg(EVT VT);
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelect() = 0;
void SelectRootInit() {
DAGSize = CurDAG->AssignTopologicalOrder();
}
/// PreprocessISelDAG - This hook allows targets to hack on the graph before
/// instruction selection starts.
virtual void PreprocessISelDAG() {}
/// PostprocessISelDAG() - This hook allows the target to hack on the graph
/// right after selection.
virtual void PostprocessISelDAG() {}
/// Select - Main hook targets implement to select a node.
virtual SDNode *Select(SDNode *N) = 0;
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// addressing mode, according to the specified constraint code. If this does
/// not match or is not implemented, return true. The resultant operands
@ -268,6 +274,8 @@ protected:
void CannotYetSelectIntrinsic(SDNode *N);
private:
void DoInstructionSelection();
void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
MachineModuleInfo *MMI,
DwarfWriter *DW,

61
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -723,9 +723,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
// code to the MachineBasicBlock.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Selection", GroupName);
InstructionSelect();
DoInstructionSelection();
} else {
InstructionSelect();
DoInstructionSelection();
}
DEBUG(dbgs() << "Selected selection DAG:\n");
@ -765,6 +765,63 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(BB->dump());
}
void SelectionDAGISel::DoInstructionSelection() {
DEBUG(errs() << "===== Instruction selection begins:\n");
PreprocessISelDAG();
// Select target instructions for the DAG.
{
// Number all nodes with a topological order and set DAGSize.
DAGSize = CurDAG->AssignTopologicalOrder();
// Create a dummy node (which is not added to allnodes), that adds
// a reference to the root node, preventing it from being deleted,
// and tracking any changes of the root.
HandleSDNode Dummy(CurDAG->getRoot());
ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
++ISelPosition;
// The AllNodes list is now topological-sorted. Visit the
// nodes by starting at the end of the list (the root of the
// graph) and preceding back toward the beginning (the entry
// node).
while (ISelPosition != CurDAG->allnodes_begin()) {
SDNode *Node = --ISelPosition;
// Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
// but there are currently some corner cases that it misses. Also, this
// makes it theoretically possible to disable the DAGCombiner.
if (Node->use_empty())
continue;
SDNode *ResNode = Select(Node);
// If node should not be replaced, continue with the next one.
if (ResNode == Node)
continue;
// Replace node.
if (ResNode)
ReplaceUses(Node, ResNode);
// If after the replacement this node is not used any more,
// remove this dead node.
if (Node->use_empty()) { // Don't delete EntryToken, etc.
ISelUpdater ISU(ISelPosition);
CurDAG->RemoveDeadNode(Node, &ISU);
}
}
CurDAG->setRoot(Dummy.getValue());
}
DEBUG(errs() << "===== Instruction selection ends:\n");
PostprocessISelDAG();
// FIXME: This shouldn't be needed, remove it.
CurDAG->RemoveDeadNodes();
}
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
MachineFunction &MF,
MachineModuleInfo *MMI,

7
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -58,8 +58,6 @@ public:
return "ARM Instruction Selection";
}
virtual void InstructionSelect();
/// getI32Imm - Return a target constant of type i32 with the specified
/// value.
inline SDValue getI32Imm(unsigned Imm) {
@ -203,11 +201,6 @@ static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
}
void ARMDAGToDAGISel::InstructionSelect() {
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
SDValue N,
SDValue &BaseReg,

15
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -159,10 +159,6 @@ namespace {
// target-specific node if it hasn't already been changed.
SDNode *Select(SDNode *N);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
virtual const char *getPassName() const {
return "Alpha DAG->DAG Pattern Instruction Selection";
}
@ -222,20 +218,11 @@ SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void AlphaDAGToDAGISel::InstructionSelect() {
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) {
if (N->isMachineOpcode())
return NULL; // Already selected.
}
DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {

10
lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
View File

@ -41,7 +41,7 @@ namespace {
BlackfinDAGToDAGISel(BlackfinTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(TM, OptLevel) {}
virtual void InstructionSelect();
virtual void PostprocessISelDAG();
virtual const char *getPassName() const {
return "Blackfin DAG->DAG Pattern Instruction Selection";
@ -72,13 +72,7 @@ FunctionPass *llvm::createBlackfinISelDag(BlackfinTargetMachine &TM,
return new BlackfinDAGToDAGISel(TM, OptLevel);
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void BlackfinDAGToDAGISel::InstructionSelect() {
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
DEBUG(errs() << "Selected selection DAG before regclass fixup:\n");
DEBUG(CurDAG->dump());
void BlackfinDAGToDAGISel::PostprocessISelDAG() {
FixRegisterClasses(*CurDAG);
}

14
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -399,10 +399,6 @@ namespace {
return false;
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
virtual const char *getPassName() const {
return "Cell SPU DAG->DAG Pattern Instruction Selection";
}
@ -420,16 +416,6 @@ namespace {
};
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void
SPUDAGToDAGISel::InstructionSelect()
{
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
/*!
\arg Op The ISD instruction operand
\arg N The address to be tested

35
lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
View File

@ -59,8 +59,6 @@ public:
SelectionDAGISel(tm),
TM(tm), Subtarget(tm.getSubtarget<MBlazeSubtarget>()) {}
virtual void InstructionSelect();
// Pass Name
virtual const char *getPassName() const {
return "MBlaze DAG->DAG Pattern Instruction Selection";
@ -96,11 +94,6 @@ private:
inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
#ifndef NDEBUG
unsigned Indent;
#endif
};
}
@ -125,20 +118,6 @@ static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
return isIntS32Immediate(Op.getNode(), Imm);
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MBlazeDAGToDAGISel::InstructionSelect() {
// Codegen the basic block.
DEBUG(errs() << "===== Instruction selection begins:\n");
DEBUG(Indent = 0);
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
}
/// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it
@ -269,17 +248,11 @@ SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) {
DebugLoc dl = Node->getDebugLoc();
// Dump information about the Node being selected
DEBUG(errs().indent(Indent) << "Selecting: ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent += 2);
DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
DEBUG(errs().indent(Indent-2) << "== ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent -= 2);
DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
return NULL;
}
@ -350,14 +323,12 @@ SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) {
// Select the default instruction
SDNode *ResNode = SelectCode(Node);
DEBUG(errs().indent(Indent-2) << "=> ");
DEBUG(errs() << "=> ");
if (ResNode == NULL || ResNode == Node)
DEBUG(Node->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DEBUG(errs() << "\n");
DEBUG(Indent -= 2);
return ResNode;
}

48
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -26,7 +26,6 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
@ -35,14 +34,6 @@
using namespace llvm;
#ifndef NDEBUG
static cl::opt<bool>
ViewRMWDAGs("view-msp430-rmw-dags", cl::Hidden,
cl::desc("Pop up a window to show isel dags after RMW preprocess"));
#else
static const bool ViewRMWDAGs = false;
#endif
STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
@ -123,7 +114,8 @@ namespace {
Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { }
virtual void InstructionSelect();
virtual void PreprocessISelDAG();
virtual void PostprocessISelDAG();
virtual const char *getPassName() const {
return "MSP430 DAG->DAG Pattern Instruction Selection";
@ -151,10 +143,6 @@ namespace {
unsigned Opc8, unsigned Opc16);
bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
#ifndef NDEBUG
unsigned Indent;
#endif
};
} // end anonymous namespace
@ -681,28 +669,11 @@ SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MSP430DAGToDAGISel::InstructionSelect() {
std::string BlockName;
if (ViewRMWDAGs)
BlockName = MF->getFunction()->getNameStr() + ":" +
BB->getBasicBlock()->getNameStr();
void MSP430DAGToDAGISel::PreprocessISelDAG() {
PreprocessForRMW();
}
if (ViewRMWDAGs) CurDAG->viewGraph("RMW preprocessed:" + BlockName);
DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
DEBUG(CurDAG->dump());
// Codegen the basic block.
DEBUG(errs() << "===== Instruction selection begins:\n");
DEBUG(Indent = 0);
SelectRoot(*CurDAG);
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
void MSP430DAGToDAGISel::PostprocessISelDAG() {
RMWStores.clear();
}
@ -710,17 +681,15 @@ SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
DebugLoc dl = Node->getDebugLoc();
// Dump information about the Node being selected
DEBUG(errs().indent(Indent) << "Selecting: ");
DEBUG(errs() << "Selecting: ");
DEBUG(Node->dump(CurDAG));
DEBUG(errs() << "\n");
DEBUG(Indent += 2);
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
DEBUG(errs().indent(Indent-2) << "== ";
DEBUG(errs() << "== ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent -= 2);
return NULL;
}
@ -808,13 +777,12 @@ SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
// Select the default instruction
SDNode *ResNode = SelectCode(Node);
DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
DEBUG(errs() << "=> ");
if (ResNode == NULL || ResNode == Node)
DEBUG(Node->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DEBUG(errs() << "\n");
DEBUG(Indent -= 2);
return ResNode;
}

35
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -59,8 +59,6 @@ public:
SelectionDAGISel(tm),
TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
virtual void InstructionSelect();
// Pass Name
virtual const char *getPassName() const {
return "MIPS DAG->DAG Pattern Instruction Selection";
@ -98,29 +96,10 @@ private:
inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
#ifndef NDEBUG
unsigned Indent;
#endif
};
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MipsDAGToDAGISel::InstructionSelect() {
// Codegen the basic block.
DEBUG(errs() << "===== Instruction selection begins:\n");
DEBUG(Indent = 0);
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
}
/// getGlobalBaseReg - Output the instructions required to put the
/// GOT address into a register.
@ -329,17 +308,11 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
DebugLoc dl = Node->getDebugLoc();
// Dump information about the Node being selected
DEBUG(errs().indent(Indent) << "Selecting: ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent += 2);
DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
DEBUG(errs().indent(Indent-2) << "== ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent -= 2);
DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
return NULL;
}
@ -547,14 +520,12 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
// Select the default instruction
SDNode *ResNode = SelectCode(Node);
DEBUG(errs().indent(Indent-2) << "=> ");
DEBUG(errs() << "=> ");
if (ResNode == NULL || ResNode == Node)
DEBUG(Node->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DEBUG(errs() << "\n");
DEBUG(Indent -= 2);
return ResNode;
}

7
lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
View File

@ -24,13 +24,6 @@ FunctionPass *llvm::createPIC16ISelDag(PIC16TargetMachine &TM) {
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void PIC16DAGToDAGISel::InstructionSelect() {
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
/// Select - Select instructions not customized! Used for
/// expanded, promoted and normal instructions.
SDNode* PIC16DAGToDAGISel::Select(SDNode *N) {

2
lib/Target/PIC16/PIC16ISelDAGToDAG.h
View File

@ -48,8 +48,6 @@ public:
return "PIC16 DAG->DAG Pattern Instruction Selection";
}
virtual void InstructionSelect();
private:
// Include the pieces autogenerated from the target description.
#include "PIC16GenDAGISel.inc"

12
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -156,10 +156,6 @@ namespace {
SDValue BuildSDIVSequence(SDNode *N);
SDValue BuildUDIVSequence(SDNode *N);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
void InsertVRSaveCode(MachineFunction &MF);
virtual const char *getPassName() const {
@ -184,14 +180,6 @@ private:
};
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void PPCDAGToDAGISel::InstructionSelect() {
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
/// InsertVRSaveCode - Once the entire function has been instruction selected,
/// all virtual registers are created and all machine instructions are built,
/// check to see if we need to save/restore VRSAVE. If so, do it.

16
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -35,7 +35,6 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
/// make the right decision when generating code for different targets.
const SparcSubtarget &Subtarget;
SparcTargetMachine& TM;
MachineBasicBlock *CurBB;
public:
explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
: SelectionDAGISel(tm),
@ -56,10 +55,6 @@ public:
char ConstraintCode,
std::vector<SDValue> &OutOps);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
virtual const char *getPassName() const {
return "SPARC DAG->DAG Pattern Instruction Selection";
}
@ -72,17 +67,8 @@ private:
};
} // end anonymous namespace
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SparcDAGToDAGISel::InstructionSelect() {
CurBB = BB;
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
MachineFunction *MF = CurBB->getParent();
MachineFunction *MF = BB->getParent();
unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
}

56
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -100,8 +100,6 @@ namespace {
Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { }
virtual void InstructionSelect();
virtual const char *getPassName() const {
return "SystemZ DAG->DAG Pattern Instruction Selection";
}
@ -152,10 +150,6 @@ namespace {
bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit);
#ifndef NDEBUG
unsigned Indent;
#endif
};
} // end anonymous namespace
@ -599,35 +593,17 @@ bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
return false;
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SystemZDAGToDAGISel::InstructionSelect() {
// Codegen the basic block.
DEBUG(errs() << "===== Instruction selection begins:\n");
DEBUG(Indent = 0);
SelectRoot(*CurDAG);
DEBUG(errs() << "===== Instruction selection ends:\n");
CurDAG->RemoveDeadNodes();
}
SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
EVT NVT = Node->getValueType(0);
DebugLoc dl = Node->getDebugLoc();
unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected
DEBUG(errs().indent(Indent) << "Selecting: ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent += 2);
DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
DEBUG(errs().indent(Indent-2) << "== ";
Node->dump(CurDAG);
errs() << "\n");
DEBUG(Indent -= 2);
DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
return NULL; // Already selected.
}
@ -693,9 +669,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
MVT::i32));
ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
@ -708,15 +682,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
MVT::i32));
ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
#ifndef NDEBUG
Indent -= 2;
#endif
return NULL;
}
case ISD::UDIVREM: {
@ -782,9 +750,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
@ -796,15 +762,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
CurDAG->getTargetConstant(SubRegIdx,
MVT::i32));
ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
DEBUG(errs().indent(Indent-2) << "=> ";
Result->dump(CurDAG);
errs() << "\n");
DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
#ifndef NDEBUG
Indent -= 2;
#endif
return NULL;
}
}
@ -812,14 +772,12 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
// Select the default instruction
SDNode *ResNode = SelectCode(Node);
DEBUG(errs().indent(Indent-2) << "=> ";
DEBUG(errs() << "=> ";
if (ResNode == NULL || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);
errs() << "\n";
);
DEBUG(Indent -= 2);
return ResNode;
}

106
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -168,14 +168,12 @@ namespace {
return "X86 DAG->DAG Instruction Selection";
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
virtual void PreprocessISelDAG();
// Include the pieces autogenerated from the target description.
#include "X86GenDAGISel.inc"
@ -208,6 +206,7 @@ namespace {
SDValue &Base, SDValue &Scale,
SDValue &Index, SDValue &Disp,
SDValue &Segment);
void PreprocessForRMW();
void PreprocessForFPConvert();
@ -286,10 +285,6 @@ namespace {
const X86InstrInfo *getInstrInfo() {
return getTargetMachine().getInstrInfo();
}
#ifndef NDEBUG
unsigned Indent;
#endif
};
}
@ -669,29 +664,14 @@ void X86DAGToDAGISel::PreprocessForFPConvert() {
}
}
/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
/// when it has created a SelectionDAG for us to codegen.
void X86DAGToDAGISel::InstructionSelect() {
const Function *F = MF->getFunction();
OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
void X86DAGToDAGISel::PreprocessISelDAG() {
OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
if (OptLevel != CodeGenOpt::None)
PreprocessForRMW();
// FIXME: This should only happen when not compiled with -O0.
PreprocessForFPConvert();
// Codegen the basic block.
#ifndef NDEBUG
DEBUG(dbgs() << "===== Instruction selection begins:\n");
Indent = 0;
#endif
SelectRoot(*CurDAG);
#ifndef NDEBUG
DEBUG(dbgs() << "===== Instruction selection ends:\n");
#endif
CurDAG->RemoveDeadNodes();
}
/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
@ -1694,24 +1674,10 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode = Node->getOpcode();
DebugLoc dl = Node->getDebugLoc();
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent, ' ') << "Selecting: ";
Node->dump(CurDAG);
dbgs() << '\n';
});
Indent += 2;
#endif
DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
if (Node->isMachineOpcode()) {
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent-2, ' ') << "== ";
Node->dump(CurDAG);
dbgs() << '\n';
});
Indent -= 2;
#endif
DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
return NULL; // Already selected.
}
@ -1807,13 +1773,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(SDValue(Node, 0), Result);
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent-2, ' ') << "=> ";
Result.getNode()->dump(CurDAG);
dbgs() << '\n';
});
#endif
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
}
// Copy the high half of the result, if it is needed.
if (!SDValue(Node, 1).use_empty()) {
@ -1836,19 +1796,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
InFlag = Result.getValue(2);
}
ReplaceUses(SDValue(Node, 1), Result);
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent-2, ' ') << "=> ";
Result.getNode()->dump(CurDAG);
dbgs() << '\n';
});
#endif
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
}
#ifndef NDEBUG
Indent -= 2;
#endif
return NULL;
}
@ -1963,13 +1913,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(SDValue(Node, 0), Result);
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent-2, ' ') << "=> ";
Result.getNode()->dump(CurDAG);
dbgs() << '\n';
});
#endif
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
}
// Copy the remainder (high) result, if it is needed.
if (!SDValue(Node, 1).use_empty()) {
@ -1993,19 +1937,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
InFlag = Result.getValue(2);
}
ReplaceUses(SDValue(Node, 1), Result);
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent-2, ' ') << "=> ";
Result.getNode()->dump(CurDAG);
dbgs() << '\n';
});
#endif
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
}
#ifndef NDEBUG
Indent -= 2;
#endif
return NULL;
}
@ -2118,17 +2051,12 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
SDNode *ResNode = SelectCode(Node);
#ifndef NDEBUG
DEBUG({
dbgs() << std::string(Indent-2, ' ') << "=> ";
if (ResNode == NULL || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);
dbgs() << '\n';
});
Indent -= 2;
#endif
DEBUG(dbgs() << "=> ";
if (ResNode == NULL || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);
dbgs() << '\n');
return ResNode;
}

11
lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -65,8 +65,6 @@ namespace {
bool SelectADDRcpii(SDNode *Op, SDValue Addr, SDValue &Base,
SDValue &Offset);
virtual void InstructionSelect();
virtual const char *getPassName() const {
return "XCore DAG->DAG Pattern Instruction Selection";
}
@ -147,15 +145,6 @@ bool XCoreDAGToDAGISel::SelectADDRcpii(SDNode *Op, SDValue Addr,
return false;
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void XCoreDAGToDAGISel::InstructionSelect() {
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
EVT NVT = N->getValueType(0);