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R600/SI: move *_Helper definitions to SIInstrFormat.td

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This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-02-16 11:28:02 +00:00
parent 0432d7964f
commit 7c52866a14
2 changed files with 66 additions and 66 deletions
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66
lib/Target/R600/SIInstrFormats.td
View File

@ -144,3 +144,69 @@ class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
class SOPC_64 <bits<7> op, string opName, list<dag> pattern> class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
: SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>; : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
op,
(outs VReg_128:$vdata),
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
asm,
[]> {
let mayLoad = 1;
let mayStore = 0;
}
class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs),
(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
asm,
[]> {
let mayStore = 1;
let mayLoad = 0;
}
class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
op,
(outs regClass:$dst),
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
i1imm:$tfe, SReg_32:$soffset),
asm,
[]> {
let mayLoad = 1;
let mayStore = 0;
}
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs regClass:$dst),
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
asm,
[]> {
let mayLoad = 1;
let mayStore = 0;
}
multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
def _IMM : SMRD <
op, 1,
(outs dstClass:$dst),
(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
asm,
[]
>;
def _SGPR : SMRD <
op, 0,
(outs dstClass:$dst),
(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
asm,
[]
>;
}

66
lib/Target/R600/SIInstrInfo.td
View File

@ -484,71 +484,5 @@ class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
} // End Uses = [EXEC] } // End Uses = [EXEC]
class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
op,
(outs VReg_128:$vdata),
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
asm,
[]> {
let mayLoad = 1;
let mayStore = 0;
}
class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
op,
(outs regClass:$dst),
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
i1imm:$tfe, SReg_32:$soffset),
asm,
[]> {
let mayLoad = 1;
let mayStore = 0;
}
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs regClass:$dst),
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
asm,
[]> {
let mayLoad = 1;
let mayStore = 0;
}
class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs),
(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
asm,
[]> {
let mayStore = 1;
let mayLoad = 0;
}
multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
def _IMM : SMRD <
op, 1,
(outs dstClass:$dst),
(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
asm,
[]
>;
def _SGPR : SMRD <
op, 0,
(outs dstClass:$dst),
(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
asm,
[]
>;
}
include "SIInstrFormats.td" include "SIInstrFormats.td"
include "SIInstructions.td" include "SIInstructions.td"