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Revert:
Author: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon Feb 23 23:04:28 2015 +0000
Fix based on post-commit comment on D7816 & rL230177 - BUILD_VECTOR operand truncation was using the the BV's output scalar type instead of the input type.
and
Author: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun Feb 22 18:17:28 2015 +0000
[DagCombiner] Generalized BuildVector Vector Concatenation
The CONCAT_VECTORS combiner pass can transform the concat of two BUILD_VECTOR nodes into a single BUILD_VECTOR node.
This patch generalises this to support any number of BUILD_VECTOR nodes, and also permits UNDEF nodes to be included as well.
This was noticed as AVX vec128 -> vec256 canonicalization sometimes creates a CONCAT_VECTOR with a real vec128 lower and an vec128 UNDEF upper.
Differential Revision: http://reviews.llvm.org/D7816
as the root cause of PR22678 which is causing an assertion inside the DAG combiner.
I'll follow up to the main thread as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
f8c57a105e
commit
7c611d59cc
@ -11430,52 +11430,36 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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}
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}
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// Fold any combination of BUILD_VECTOR or UNDEF nodes into one BUILD_VECTOR.
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// We have already tested above for an UNDEF only concatenation.
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// fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
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// -> (BUILD_VECTOR A, B, ..., C, D, ...)
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auto IsBuildVectorOrUndef = [](const SDValue &Op) {
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return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
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};
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bool AllBuildVectorsOrUndefs =
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std::all_of(N->op_begin(), N->op_end(), IsBuildVectorOrUndef);
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if (AllBuildVectorsOrUndefs) {
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if (N->getNumOperands() == 2 &&
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N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
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N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
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EVT VT = N->getValueType(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SmallVector<SDValue, 8> Opnds;
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EVT SVT = VT.getScalarType();
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unsigned BuildVecNumElts = N0.getNumOperands();
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EVT MinVT = SVT;
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if (!SVT.isFloatingPoint())
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EVT SclTy0 = N0.getOperand(0)->getValueType(0);
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EVT SclTy1 = N1.getOperand(0)->getValueType(0);
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if (SclTy0.isFloatingPoint()) {
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N0.getOperand(i));
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N1.getOperand(i));
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} else {
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// If BUILD_VECTOR are from built from integer, they may have different
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// operand types. Get the smaller type and truncate all operands to it.
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for (const SDValue &Op : N->ops())
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if (ISD::BUILD_VECTOR == Op.getOpcode()) {
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EVT OpSVT = Op.getOperand(0)->getValueType(0);
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MinVT = MinVT.bitsLE(OpSVT) ? MinVT : OpSVT;
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}
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for (const SDValue &Op : N->ops()) {
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EVT OpVT = Op.getValueType();
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unsigned NumElts = OpVT.getVectorNumElements();
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if (ISD::UNDEF == Op.getOpcode())
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for (unsigned i = 0; i != NumElts; ++i)
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Opnds.push_back(DAG.getUNDEF(MinVT));
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if (ISD::BUILD_VECTOR == Op.getOpcode()) {
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if (SVT.isFloatingPoint()) {
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assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch");
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for (unsigned i = 0; i != NumElts; ++i)
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Opnds.push_back(Op.getOperand(i));
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} else {
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for (unsigned i = 0; i != NumElts; ++i)
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Opnds.push_back(
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DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i)));
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}
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}
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EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
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N0.getOperand(i)));
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
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N1.getOperand(i)));
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}
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assert(VT.getVectorNumElements() == Opnds.size() &&
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"Concat vector type mismatch");
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
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}
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@ -358,16 +358,22 @@ define <8 x i32> @shuf_zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone
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;
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; AVX1-LABEL: shuf_zext_8i16_to_8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
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; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
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; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuf_zext_8i16_to_8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: # kill
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; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpbroadcastw %xmm1, %xmm1
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; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
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; AVX2-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
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; AVX2-NEXT: vpunpcklwd{{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%B = shufflevector <8 x i16> %A, <8 x i16> zeroinitializer, <16 x i32> <i32 0, i32 8, i32 1, i32 8, i32 2, i32 8, i32 3, i32 8, i32 4, i32 8, i32 5, i32 8, i32 6, i32 8, i32 7, i32 8>
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@ -404,17 +410,22 @@ define <4 x i64> @shuf_zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone
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;
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; AVX1-LABEL: shuf_zext_4i32_to_4i64:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero
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; AVX1-NEXT: vxorpd %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,1],xmm1[0,0]
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; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,0,3,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuf_zext_4i32_to_4i64:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: # kill
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; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; AVX2-NEXT: xorl %eax, %eax
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; AVX2-NEXT: vmovd %eax, %xmm1
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; AVX2-NEXT: vpbroadcastd %xmm1, %ymm1
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
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; AVX2-NEXT: retq
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entry:
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%B = shufflevector <4 x i32> %A, <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 4, i32 1, i32 4, i32 2, i32 4, i32 3, i32 4>
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