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Replace a few more "fall through" comments with LLVM_FALLTHROUGH

Browse Source 
Follow up to r278902. I had missed "fall through", with a space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278970 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Bogner 2016-08-17 20:30:52 +00:00
parent 3ed44cd787
commit 7d7a23e700
52 changed files with 209 additions and 161 deletions
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4
examples/BrainF/BrainF.cpp
View File

@ -339,7 +339,7 @@ void BrainF::readloop(PHINode *phi, BasicBlock *oldbb, BasicBlock *testbb,
switch(c) {
case '-':
direction = -1;
// Fall through
LLVM_FALLTHROUGH;
case '+':
if (cursym == SYM_CHANGE) {
@ -360,7 +360,7 @@ void BrainF::readloop(PHINode *phi, BasicBlock *oldbb, BasicBlock *testbb,
case '<':
direction = -1;
// Fall through
LLVM_FALLTHROUGH;
case '>':
if (cursym == SYM_MOVE) {

2
lib/Analysis/BasicAliasAnalysis.cpp
View File

@ -227,7 +227,7 @@ static bool isObjectSize(const Value *V, uint64_t Size, const DataLayout &DL,
Offset = 0;
return V;
}
// FALL THROUGH.
LLVM_FALLTHROUGH;
case Instruction::Add:
V = GetLinearExpression(BOp->getOperand(0), Scale, Offset, ZExtBits,
SExtBits, DL, Depth + 1, AC, DT, NSW, NUW);

2
lib/Analysis/MemoryDependenceAnalysis.cpp
View File

@ -1010,7 +1010,7 @@ SortNonLocalDepInfoCache(MemoryDependenceResults::NonLocalDepInfo &Cache,
MemoryDependenceResults::NonLocalDepInfo::iterator Entry =
std::upper_bound(Cache.begin(), Cache.end() - 1, Val);
Cache.insert(Entry, Val);
// FALL THROUGH.
LLVM_FALLTHROUGH;
}
case 1:
// One new entry, Just insert the new value at the appropriate position.

12
lib/Analysis/ScalarEvolution.cpp
View File

@ -4288,7 +4288,7 @@ const SCEV *ScalarEvolution::createNodeForSelectOrPHI(Instruction *I,
case ICmpInst::ICMP_SLT:
case ICmpInst::ICMP_SLE:
std::swap(LHS, RHS);
// fall through
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_SGT:
case ICmpInst::ICMP_SGE:
// a >s b ? a+x : b+x -> smax(a, b)+x
@ -4311,7 +4311,7 @@ const SCEV *ScalarEvolution::createNodeForSelectOrPHI(Instruction *I,
case ICmpInst::ICMP_ULT:
case ICmpInst::ICMP_ULE:
std::swap(LHS, RHS);
// fall through
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_UGT:
case ICmpInst::ICMP_UGE:
// a >u b ? a+x : b+x -> umax(a, b)+x
@ -8502,7 +8502,7 @@ static bool IsKnownPredicateViaMinOrMax(ScalarEvolution &SE,
case ICmpInst::ICMP_SGE:
std::swap(LHS, RHS);
// fall through
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_SLE:
return
// min(A, ...) <= A
@ -8512,7 +8512,7 @@ static bool IsKnownPredicateViaMinOrMax(ScalarEvolution &SE,
case ICmpInst::ICMP_UGE:
std::swap(LHS, RHS);
// fall through
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_ULE:
return
// min(A, ...) <= A
@ -9858,8 +9858,10 @@ ScalarEvolution::computeBlockDisposition(const SCEV *S, const BasicBlock *BB) {
const SCEVAddRecExpr *AR = cast<SCEVAddRecExpr>(S);
if (!DT.dominates(AR->getLoop()->getHeader(), BB))
return DoesNotDominateBlock;
// Fall through into SCEVNAryExpr handling.
LLVM_FALLTHROUGH;
}
// FALL THROUGH into SCEVNAryExpr handling.
case scAddExpr:
case scMulExpr:
case scUMaxExpr:

1
lib/Analysis/TargetLibraryInfo.cpp
View File

@ -324,6 +324,7 @@ static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T,
// on Linux.
//
// Fall through to disable all of them.
LLVM_FALLTHROUGH;
default:
TLI.setUnavailable(LibFunc::exp10);
TLI.setUnavailable(LibFunc::exp10f);

5
lib/Analysis/ValueTracking.cpp
View File

@ -1012,7 +1012,8 @@ static void computeKnownBitsFromOperator(const Operator *I, APInt &KnownZero,
case Instruction::PtrToInt:
case Instruction::IntToPtr:
case Instruction::AddrSpaceCast: // Pointers could be different sizes.
// FALL THROUGH and handle them the same as zext/trunc.
// Fall through and handle them the same as zext/trunc.
LLVM_FALLTHROUGH;
case Instruction::ZExt:
case Instruction::Trunc: {
Type *SrcTy = I->getOperand(0)->getType();
@ -2559,7 +2560,7 @@ bool llvm::CannotBeOrderedLessThanZero(const Value *V,
// x*x is always non-negative or a NaN.
if (I->getOperand(0) == I->getOperand(1))
return true;
// Fall through
LLVM_FALLTHROUGH;
case Instruction::FAdd:
case Instruction::FDiv:
case Instruction::FRem:

2
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -1784,7 +1784,7 @@ const MCExpr *AsmPrinter::lowerConstant(const Constant *CV) {
// expression properly. This is important for differences between
// blockaddress labels. Since the two labels are in the same function, it
// is reasonable to treat their delta as a 32-bit value.
// FALL THROUGH.
LLVM_FALLTHROUGH;
case Instruction::BitCast:
return lowerConstant(CE->getOperand(0));

32
lib/CodeGen/AsmPrinter/DIE.cpp
View File

@ -247,17 +247,17 @@ void DIEInteger::EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const {
// FIXME: Is there a better way to do this?
Asm->OutStreamer->AddBlankLine();
return;
case dwarf::DW_FORM_flag: // Fall thru
case dwarf::DW_FORM_ref1: // Fall thru
case dwarf::DW_FORM_flag: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_ref1: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data1: Size = 1; break;
case dwarf::DW_FORM_ref2: // Fall thru
case dwarf::DW_FORM_ref2: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data2: Size = 2; break;
case dwarf::DW_FORM_sec_offset: // Fall thru
case dwarf::DW_FORM_strp: // Fall thru
case dwarf::DW_FORM_ref4: // Fall thru
case dwarf::DW_FORM_sec_offset: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_strp: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_ref4: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data4: Size = 4; break;
case dwarf::DW_FORM_ref8: // Fall thru
case dwarf::DW_FORM_ref_sig8: // Fall thru
case dwarf::DW_FORM_ref8: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_ref_sig8: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data8: Size = 8; break;
case dwarf::DW_FORM_GNU_str_index: Asm->EmitULEB128(Integer); return;
case dwarf::DW_FORM_GNU_addr_index: Asm->EmitULEB128(Integer); return;
@ -279,17 +279,17 @@ void DIEInteger::EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const {
unsigned DIEInteger::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const {
switch (Form) {
case dwarf::DW_FORM_flag_present: return 0;
case dwarf::DW_FORM_flag: // Fall thru
case dwarf::DW_FORM_ref1: // Fall thru
case dwarf::DW_FORM_flag: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_ref1: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data1: return sizeof(int8_t);
case dwarf::DW_FORM_ref2: // Fall thru
case dwarf::DW_FORM_ref2: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data2: return sizeof(int16_t);
case dwarf::DW_FORM_sec_offset: // Fall thru
case dwarf::DW_FORM_strp: // Fall thru
case dwarf::DW_FORM_ref4: // Fall thru
case dwarf::DW_FORM_sec_offset: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_strp: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_ref4: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data4: return sizeof(int32_t);
case dwarf::DW_FORM_ref8: // Fall thru
case dwarf::DW_FORM_ref_sig8: // Fall thru
case dwarf::DW_FORM_ref8: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_ref_sig8: LLVM_FALLTHROUGH;
case dwarf::DW_FORM_data8: return sizeof(int64_t);
case dwarf::DW_FORM_GNU_str_index: return getULEB128Size(Integer);
case dwarf::DW_FORM_GNU_addr_index: return getULEB128Size(Integer);

8
lib/CodeGen/RegAllocFast.cpp
View File

@ -360,7 +360,7 @@ void RAFast::usePhysReg(MachineOperand &MO) {
break;
case regReserved:
PhysRegState[PhysReg] = regFree;
// Fall through
LLVM_FALLTHROUGH;
case regFree:
MO.setIsKill();
return;
@ -389,7 +389,7 @@ void RAFast::usePhysReg(MachineOperand &MO) {
assert((TRI->isSuperRegister(PhysReg, Alias) ||
TRI->isSuperRegister(Alias, PhysReg)) &&
"Instruction is not using a subregister of a reserved register");
// Fall through.
LLVM_FALLTHROUGH;
case regFree:
if (TRI->isSuperRegister(PhysReg, Alias)) {
// Leave the superregister in the working set.
@ -421,7 +421,7 @@ void RAFast::definePhysReg(MachineInstr &MI, unsigned PhysReg,
break;
default:
spillVirtReg(MI, VirtReg);
// Fall through.
LLVM_FALLTHROUGH;
case regFree:
case regReserved:
PhysRegState[PhysReg] = NewState;
@ -437,7 +437,7 @@ void RAFast::definePhysReg(MachineInstr &MI, unsigned PhysReg,
break;
default:
spillVirtReg(MI, VirtReg);
// Fall through.
LLVM_FALLTHROUGH;
case regFree:
case regReserved:
PhysRegState[Alias] = regDisabled;

4
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -2231,8 +2231,8 @@ void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
if ((OtherV.WriteLanes & ~V.ValidLanes) != 0 && TrackSubRegLiveness)
OtherV.ErasableImplicitDef = false;
OtherV.Pruned = true;
LLVM_FALLTHROUGH;
}
// Fall through.
default:
// This value number needs to go in the final joined live range.
Assignments[ValNo] = NewVNInfo.size();
@ -2517,7 +2517,7 @@ void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
// make it appear like an unused value number.
VNI->markUnused();
DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n');
// FALL THROUGH.
LLVM_FALLTHROUGH;
}
case CR_Erase: {

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1579,7 +1579,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
Changed = true;
break;
}
// Fall thru
LLVM_FALLTHROUGH;
default:
// Only add if it isn't already in the list.

4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1123,12 +1123,12 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
ReplaceNode(Node, ResultVals.data());
return;
}
LLVM_FALLTHROUGH;
}
// FALL THROUGH
case TargetLowering::Expand:
if (ExpandNode(Node))
return;
// FALL THROUGH
LLVM_FALLTHROUGH;
case TargetLowering::LibCall:
ConvertNodeToLibcall(Node);
return;

2
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -362,7 +362,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
Result = Tmp1;
break;
}
// FALL THROUGH
LLVM_FALLTHROUGH;
}
case TargetLowering::Expand:
Result = Expand(Op);

14
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1943,29 +1943,29 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
default: break;
case ISD::SETEQ: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
LLVM_FALLTHROUGH;
case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, dl, VT);
case ISD::SETNE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
LLVM_FALLTHROUGH;
case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpLessThan, dl, VT);
case ISD::SETLT: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
LLVM_FALLTHROUGH;
case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, dl, VT);
case ISD::SETGT: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
LLVM_FALLTHROUGH;
case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, dl, VT);
case ISD::SETLE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
LLVM_FALLTHROUGH;
case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
R==APFloat::cmpEqual, dl, VT);
case ISD::SETGE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT);
// fall through
LLVM_FALLTHROUGH;
case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpEqual, dl, VT);
case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, dl, VT);
@ -2350,8 +2350,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
}
}
}
LLVM_FALLTHROUGH;
}
// fall through
case ISD::ADD:
case ISD::ADDE: {
// Output known-0 bits are known if clear or set in both the low clear bits

3
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -2482,7 +2482,7 @@ static bool isVectorReductionOp(const User *I) {
if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
if (FPOp->getFastMathFlags().unsafeAlgebra())
break;
// Fall through.
LLVM_FALLTHROUGH;
default:
return false;
}
@ -9243,4 +9243,3 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);
}
}

4
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1147,8 +1147,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// See if the operation should be performed at a smaller bit width.
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
return true;
LLVM_FALLTHROUGH;
}
// FALL THROUGH
default:
// Just use computeKnownBits to compute output bits.
TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
@ -2301,7 +2301,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Ops.push_back(Op);
return;
}
// fall through
LLVM_FALLTHROUGH;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': { // Relocatable Constant

2
lib/Fuzzer/FuzzerMutate.cpp
View File

@ -286,7 +286,7 @@ size_t MutationDispatcher::Mutate_CrossOver(uint8_t *Data, size_t Size,
NewSize = InsertPartOf(O.data(), O.size(), U.data(), U.size(), MaxSize);
if (NewSize)
break;
// Fallthrough
LLVM_FALLTHROUGH;
case 2:
NewSize = CopyPartOf(O.data(), O.size(), U.data(), U.size());
break;

6
lib/IR/Function.cpp
View File

@ -748,9 +748,9 @@ static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
case IIT_EMPTYSTRUCT:
OutputTable.push_back(IITDescriptor::get(IITDescriptor::Struct, 0));
return;
case IIT_STRUCT5: ++StructElts; // FALL THROUGH.
case IIT_STRUCT4: ++StructElts; // FALL THROUGH.
case IIT_STRUCT3: ++StructElts; // FALL THROUGH.
case IIT_STRUCT5: ++StructElts; LLVM_FALLTHROUGH;
case IIT_STRUCT4: ++StructElts; LLVM_FALLTHROUGH;
case IIT_STRUCT3: ++StructElts; LLVM_FALLTHROUGH;
case IIT_STRUCT2: {
OutputTable.push_back(IITDescriptor::get(IITDescriptor::Struct,StructElts));

1
lib/MC/MCObjectFileInfo.cpp
View File

@ -311,6 +311,7 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const Triple &T) {
if (Ctx->getAsmInfo()->getExceptionHandlingType() == ExceptionHandling::ARM)
break;
// Fallthrough if not using EHABI
LLVM_FALLTHROUGH;
case Triple::ppc:
case Triple::x86:
PersonalityEncoding = PositionIndependent

6
lib/Support/CommandLine.cpp
View File

@ -1228,7 +1228,7 @@ bool CommandLineParser::ParseCommandLineOptions(int argc,
switch (PositionalOpts[i]->getNumOccurrencesFlag()) {
case cl::Optional:
Done = true; // Optional arguments want _at most_ one value
// FALL THROUGH
LLVM_FALLTHROUGH;
case cl::ZeroOrMore: // Zero or more will take all they can get...
case cl::OneOrMore: // One or more will take all they can get...
ProvidePositionalOption(PositionalOpts[i],
@ -1282,7 +1282,7 @@ bool CommandLineParser::ParseCommandLineOptions(int argc,
Opt.second->error("must be specified at least once!");
ErrorParsing = true;
}
// Fall through
LLVM_FALLTHROUGH;
default:
break;
}
@ -1337,7 +1337,7 @@ bool Option::addOccurrence(unsigned pos, StringRef ArgName, StringRef Value,
case Required:
if (NumOccurrences > 1)
return error("must occur exactly one time!", ArgName);
// Fall through
LLVM_FALLTHROUGH;
case OneOrMore:
case ZeroOrMore:
case ConsumeAfter:

4
lib/Support/FoldingSet.cpp
View File

@ -127,8 +127,8 @@ void FoldingSetNodeID::AddString(StringRef String) {
// Pos will have overshot size by 4 - #bytes left over.
// No need to take endianness into account here - this is always executed.
switch (Pos - Size) {
case 1: V = (V << 8) | (unsigned char)String[Size - 3]; // Fall thru.
case 2: V = (V << 8) | (unsigned char)String[Size - 2]; // Fall thru.
case 1: V = (V << 8) | (unsigned char)String[Size - 3]; LLVM_FALLTHROUGH;
case 2: V = (V << 8) | (unsigned char)String[Size - 2]; LLVM_FALLTHROUGH;
case 3: V = (V << 8) | (unsigned char)String[Size - 1]; break;
default: return; // Nothing left.
}

8
lib/Support/raw_ostream.cpp
View File

@ -344,10 +344,10 @@ void raw_ostream::copy_to_buffer(const char *Ptr, size_t Size) {
// Handle short strings specially, memcpy isn't very good at very short
// strings.
switch (Size) {
case 4: OutBufCur[3] = Ptr[3]; // FALL THROUGH
case 3: OutBufCur[2] = Ptr[2]; // FALL THROUGH
case 2: OutBufCur[1] = Ptr[1]; // FALL THROUGH
case 1: OutBufCur[0] = Ptr[0]; // FALL THROUGH
case 4: OutBufCur[3] = Ptr[3]; LLVM_FALLTHROUGH;
case 3: OutBufCur[2] = Ptr[2]; LLVM_FALLTHROUGH;
case 2: OutBufCur[1] = Ptr[1]; LLVM_FALLTHROUGH;
case 1: OutBufCur[0] = Ptr[0]; LLVM_FALLTHROUGH;
case 0: break;
default:
memcpy(OutBufCur, Ptr, Size);

2
lib/TableGen/TGLexer.cpp
View File

@ -222,7 +222,7 @@ tgtok::TokKind TGLexer::LexString() {
case '\0':
if (CurPtr == CurBuf.end())
return ReturnError(StrStart, "End of file in string literal");
// FALL THROUGH
LLVM_FALLTHROUGH;
default:
return ReturnError(CurPtr, "invalid escape in string literal");
}

2
lib/Target/AArch64/AArch64ConditionalCompares.cpp
View File

@ -329,7 +329,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
++NumImmRangeRejs;
return nullptr;
}
// Fall through.
LLVM_FALLTHROUGH;
case AArch64::SUBSWrr:
case AArch64::SUBSXrr:
case AArch64::ADDSWrr:

2
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -7057,7 +7057,7 @@ bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
// trunc(sext ty1 to ty2) to ty1.
if (Instr->getType() == Ext->getOperand(0)->getType())
continue;
// FALL THROUGH.
LLVM_FALLTHROUGH;
default:
return false;
}

10
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
View File

@ -286,7 +286,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
// Evergreen / Northern Islands
switch (MF.getFunction()->getCallingConv()) {
default: // Fall through
default: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
@ -295,9 +295,9 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
} else {
// R600 / R700
switch (MF.getFunction()->getCallingConv()) {
default: // Fall through
case CallingConv::AMDGPU_GS: // Fall through
case CallingConv::AMDGPU_CS: // Fall through
default: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
}
@ -574,7 +574,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
static unsigned getRsrcReg(CallingConv::ID CallConv) {
switch (CallConv) {
default: // Fall through
default: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;

1
lib/Target/ARM/ARMFastISel.cpp
View File

@ -1868,6 +1868,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
// Fall through to soft float variant, variadic functions don't
// use hard floating point ABI.
LLVM_FALLTHROUGH;
case CallingConv::ARM_AAPCS:
return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
case CallingConv::ARM_APCS:

4
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -8659,7 +8659,7 @@ static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
// (zext cc) can never be the all ones value.
if (AllOnes)
return false;
// Fall through.
LLVM_FALLTHROUGH;
case ISD::SIGN_EXTEND: {
SDLoc dl(N);
EVT VT = N->getValueType(0);
@ -11409,7 +11409,7 @@ bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
case 1:
if (Subtarget->isThumb1Only())
return false;
// FALL THROUGH.
LLVM_FALLTHROUGH;
default:
// ARM doesn't support any R+R*scale+imm addr modes.
if (AM.BaseOffs)

6
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1432,7 +1432,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
case ARM::STC_POST:
case ARM::STCL_POST:
imm |= U << 8;
// fall through.
LLVM_FALLTHROUGH;
default:
// The 'option' variant doesn't encode 'U' in the immediate since
// the immediate is unsigned [0,255].
@ -2555,6 +2555,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
break;
}
// Fall through to handle the register offset variant.
LLVM_FALLTHROUGH;
case ARM::VLD1d8wb_fixed:
case ARM::VLD1d16wb_fixed:
case ARM::VLD1d32wb_fixed:
@ -4157,7 +4158,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
case 0x93: // faultmask_ns
if (!(FeatureBits[ARM::HasV8MMainlineOps]))
return MCDisassembler::Fail;
// fall through
LLVM_FALLTHROUGH;
case 10: // msplim
case 11: // psplim
case 0x88: // msp_ns
@ -5310,4 +5311,3 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
return S;
}

4
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -630,7 +630,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
case ARM::fixup_arm_pcrel_10:
Value = Value - 4; // ARM fixups offset by an additional word and don't
// need to adjust for the half-word ordering.
// Fall through.
LLVM_FALLTHROUGH;
case ARM::fixup_t2_pcrel_10: {
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
Value = Value - 4;
@ -657,7 +657,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
case ARM::fixup_arm_pcrel_9:
Value = Value - 4; // ARM fixups offset by an additional word and don't
// need to adjust for the half-word ordering.
// Fall through.
LLVM_FALLTHROUGH;
case ARM::fixup_t2_pcrel_9: {
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
Value = Value - 4;

2
lib/Target/Hexagon/HexagonRDFOpt.cpp
View File

@ -116,8 +116,8 @@ bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
const MachineOperand &A = MI->getOperand(2);
if (!A.isImm() || A.getImm() != 0)
return false;
LLVM_FALLTHROUGH;
}
// Fall through.
case Hexagon::A2_tfr: {
const MachineOperand &DstOp = MI->getOperand(0);
const MachineOperand &SrcOp = MI->getOperand(1);

1
lib/Target/Hexagon/HexagonSplitDouble.cpp
View File

@ -337,6 +337,7 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
if (V == 0 || V == -1)
return 10;
// Fall through into A2_combinew.
LLVM_FALLTHROUGH;
}
case Hexagon::A2_combinew:
return 2;

2
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -1606,7 +1606,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
case Mips::BBIT1:
case Mips::BBIT132:
assert(hasCnMips() && "instruction only valid for octeon cpus");
// Fall through
LLVM_FALLTHROUGH;
case Mips::BEQ:
case Mips::BNE:

2
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
View File

@ -2124,7 +2124,7 @@ NVPTXAsmPrinter::lowerConstantForGV(const Constant *CV, bool ProcessingGeneric)
// expression properly. This is important for differences between
// blockaddress labels. Since the two labels are in the same function, it
// is reasonable to treat their delta as a 32-bit value.
// FALL THROUGH.
LLVM_FALLTHROUGH;
case Instruction::BitCast:
return lowerConstantForGV(CE->getOperand(0), ProcessingGeneric);

26
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -118,19 +118,19 @@ static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
case SPCC::CPCC_A: return SPCC::CPCC_N;
case SPCC::CPCC_N: return SPCC::CPCC_A;
case SPCC::CPCC_3: // Fall through
case SPCC::CPCC_2: // Fall through
case SPCC::CPCC_23: // Fall through
case SPCC::CPCC_1: // Fall through
case SPCC::CPCC_13: // Fall through
case SPCC::CPCC_12: // Fall through
case SPCC::CPCC_123: // Fall through
case SPCC::CPCC_0: // Fall through
case SPCC::CPCC_03: // Fall through
case SPCC::CPCC_02: // Fall through
case SPCC::CPCC_023: // Fall through
case SPCC::CPCC_01: // Fall through
case SPCC::CPCC_013: // Fall through
case SPCC::CPCC_3: LLVM_FALLTHROUGH;
case SPCC::CPCC_2: LLVM_FALLTHROUGH;
case SPCC::CPCC_23: LLVM_FALLTHROUGH;
case SPCC::CPCC_1: LLVM_FALLTHROUGH;
case SPCC::CPCC_13: LLVM_FALLTHROUGH;
case SPCC::CPCC_12: LLVM_FALLTHROUGH;
case SPCC::CPCC_123: LLVM_FALLTHROUGH;
case SPCC::CPCC_0: LLVM_FALLTHROUGH;
case SPCC::CPCC_03: LLVM_FALLTHROUGH;
case SPCC::CPCC_02: LLVM_FALLTHROUGH;
case SPCC::CPCC_023: LLVM_FALLTHROUGH;
case SPCC::CPCC_01: LLVM_FALLTHROUGH;
case SPCC::CPCC_013: LLVM_FALLTHROUGH;
case SPCC::CPCC_012:
// "Opposite" code is not meaningful, as we don't know
// what the CoProc condition means here. The cond-code will

4
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -832,7 +832,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
RxSBG.Input = N.getOperand(0);
return true;
}
// Fall through.
LLVM_FALLTHROUGH;
case ISD::SIGN_EXTEND: {
// Check that the extension bits are don't-care (i.e. are masked out
@ -1265,7 +1265,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
if (Node->getOperand(1).getOpcode() != ISD::Constant)
if (tryRxSBG(Node, SystemZ::RNSBG))
return;
// Fall through.
LLVM_FALLTHROUGH;
case ISD::ROTL:
case ISD::SHL:
case ISD::SRL:

118
lib/Target/X86/InstPrinter/X86InstComments.cpp
View File

@ -382,7 +382,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VBLENDPDrri:
case X86::VBLENDPDYrri:
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::BLENDPDrmi:
case X86::VBLENDPDrmi:
case X86::VBLENDPDYrmi:
@ -398,7 +398,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VBLENDPSrri:
case X86::VBLENDPSYrri:
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::BLENDPSrmi:
case X86::VBLENDPSrmi:
case X86::VBLENDPSYrmi:
@ -414,7 +414,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VPBLENDWrri:
case X86::VPBLENDWYrri:
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::PBLENDWrmi:
case X86::VPBLENDWrmi:
case X86::VPBLENDWYrmi:
@ -429,7 +429,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VPBLENDDrri:
case X86::VPBLENDDYrri:
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::VPBLENDDrmi:
case X86::VPBLENDDYrmi:
if (MI->getOperand(NumOperands - 1).isImm())
@ -444,7 +444,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VINSERTPSrr:
case X86::VINSERTPSZrr:
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::INSERTPSrm:
case X86::VINSERTPSrm:
case X86::VINSERTPSZrm:
@ -507,7 +507,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_MOVDUP(MOVSLDUP, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_MOVDUP(MOVSLDUP, m)
DestName = getRegName(MI->getOperand(0).getReg());
DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
@ -515,7 +516,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_MOVDUP(MOVSHDUP, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_MOVDUP(MOVSHDUP, m)
DestName = getRegName(MI->getOperand(0).getReg());
DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
@ -523,7 +525,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_MOVDUP(MOVDDUP, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_MOVDUP(MOVDDUP, m)
DestName = getRegName(MI->getOperand(0).getReg());
DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
@ -566,7 +569,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_SHUF(PALIGNR, rri)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_SHUF(PALIGNR, rmi)
Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@ -578,7 +582,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_SHUF(PSHUFD, ri)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_SHUF(PSHUFD, mi)
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
@ -589,7 +594,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_SHUF(PSHUFHW, ri)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_SHUF(PSHUFHW, mi)
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
@ -600,7 +606,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_SHUF(PSHUFLW, ri)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_SHUF(PSHUFLW, mi)
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
@ -611,7 +618,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PSHUFWri:
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::MMX_PSHUFWmi:
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
@ -622,7 +630,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::PSWAPDrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::PSWAPDrm:
DestName = getRegName(MI->getOperand(0).getReg());
DecodePSWAPMask(MVT::v2i32, ShuffleMask);
@ -632,7 +641,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PUNPCKHBWirr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHBW, m)
case X86::MMX_PUNPCKHBWirm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -644,7 +654,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PUNPCKHWDirr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHWD, m)
case X86::MMX_PUNPCKHWDirm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -656,7 +667,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PUNPCKHDQirr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHDQ, m)
case X86::MMX_PUNPCKHDQirm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -667,7 +679,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_UNPCK(PUNPCKHQDQ, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKHQDQ, m)
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@ -678,7 +691,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PUNPCKLBWirr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLBW, m)
case X86::MMX_PUNPCKLBWirm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -690,7 +704,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PUNPCKLWDirr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLWD, m)
case X86::MMX_PUNPCKLWDirm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -702,7 +717,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MMX_PUNPCKLDQirr:
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLDQ, m)
case X86::MMX_PUNPCKLDQirm:
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -713,7 +729,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_UNPCK(PUNPCKLQDQ, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(PUNPCKLQDQ, m)
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@ -723,7 +740,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_SHUF(SHUFPD, rri)
Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_SHUF(SHUFPD, rmi)
if (MI->getOperand(NumOperands - 1).isImm())
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
@ -736,7 +754,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_SHUF(SHUFPS, rri)
Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_SHUF(SHUFPS, rmi)
if (MI->getOperand(NumOperands - 1).isImm())
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
@ -749,7 +768,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_VSHUF(64X2, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_VSHUF(64X2, m)
decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0),
MI->getOperand(NumOperands - 1).getImm(),
@ -761,7 +781,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_VSHUF(32X4, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_VSHUF(32X4, m)
decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0),
MI->getOperand(NumOperands - 1).getImm(),
@ -773,7 +794,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_UNPCK(UNPCKLPD, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(UNPCKLPD, m)
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -783,7 +805,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_UNPCK(UNPCKLPS, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(UNPCKLPS, m)
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -793,7 +816,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_UNPCK(UNPCKHPD, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(UNPCKHPD, m)
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -803,7 +827,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_UNPCK(UNPCKHPS, r)
Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
RegForm = true;
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_UNPCK(UNPCKHPS, m)
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
@ -812,7 +837,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_VPERMILPI(PERMILPS, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_VPERMILPI(PERMILPS, m)
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
@ -823,7 +849,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_VPERMILPI(PERMILPD, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_VPERMILPI(PERMILPD, m)
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
@ -835,7 +862,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VPERM2F128rr:
case X86::VPERM2I128rr:
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::VPERM2F128rm:
case X86::VPERM2I128rm:
// For instruction comments purpose, assume the 256-bit vector is v4i64.
@ -849,7 +877,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_VPERM(PERMPD, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_VPERM(PERMPD, m)
if (MI->getOperand(NumOperands - 1).isImm())
DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0),
@ -860,7 +889,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_VPERM(PERMQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_VPERM(PERMQ, m)
if (MI->getOperand(NumOperands - 1).isImm())
DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0),
@ -874,7 +904,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VMOVSDZrr:
Src2Name = getRegName(MI->getOperand(2).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::MOVSDrm:
case X86::VMOVSDrm:
case X86::VMOVSDZrm:
@ -887,7 +918,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VMOVSSZrr:
Src2Name = getRegName(MI->getOperand(2).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::MOVSSrm:
case X86::VMOVSSrm:
case X86::VMOVSSZrm:
@ -901,7 +933,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VMOVZPQILo2PQIrr:
case X86::VMOVZPQILo2PQIZrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
case X86::MOVQI2PQIrm:
case X86::MOVZQI2PQIrm:
case X86::MOVZPQILo2PQIrm:
@ -954,7 +987,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXBD, r)
CASE_PMOVZX(PMOVZXBQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_PMOVZX(PMOVZXBW, m)
CASE_PMOVZX(PMOVZXBD, m)
CASE_PMOVZX(PMOVZXBQ, m)
@ -965,7 +999,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXWD, r)
CASE_PMOVZX(PMOVZXWQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_PMOVZX(PMOVZXWD, m)
CASE_PMOVZX(PMOVZXWQ, m)
DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask);
@ -974,7 +1009,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXDQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
LLVM_FALLTHROUGH;
CASE_PMOVZX(PMOVZXDQ, m)
DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());

4
lib/Target/X86/X86FastISel.cpp
View File

@ -2969,7 +2969,7 @@ bool X86FastISel::fastLowerArguments() {
default: llvm_unreachable("Unexpected value type.");
case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
case MVT::f32: // fall-through
case MVT::f32: LLVM_FALLTHROUGH;
case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
}
unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
@ -3508,7 +3508,7 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
unsigned Opc = 0;
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type");
case MVT::i1: VT = MVT::i8; // fall-through
case MVT::i1: VT = MVT::i8; LLVM_FALLTHROUGH;
case MVT::i8: Opc = X86::MOV8ri; break;
case MVT::i16: Opc = X86::MOV16ri; break;
case MVT::i32: Opc = X86::MOV32ri; break;

2
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1234,7 +1234,7 @@ bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
case ISD::UMUL_LOHI:
// A mul_lohi where we need the low part can be folded as a plain multiply.
if (N.getResNo() != 0) break;
// FALL THROUGH
LLVM_FALLTHROUGH;
case ISD::MUL:
case X86ISD::MUL_IMM:
// X*[3,5,9] -> X+X*[2,4,8]

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -15028,7 +15028,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
if (!Subtarget.hasBMI() || !isAndn || !isLegalAndnType)
break;
}
// FALL THROUGH
LLVM_FALLTHROUGH;
case ISD::SUB:
case ISD::OR:
case ISD::XOR:
@ -27635,7 +27635,7 @@ static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
break;
assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
"Invalid use of SETCC_CARRY!");
// FALL THROUGH
LLVM_FALLTHROUGH;
case X86ISD::SETCC:
// Set the condition code or opposite one if necessary.
CC = X86::CondCode(SetCC.getConstantOperandVal(0));
@ -32229,7 +32229,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::VR64RegClass);
case 'Y': // SSE_REGS if SSE2 allowed
if (!Subtarget.hasSSE2()) break;
// FALL THROUGH.
LLVM_FALLTHROUGH;
case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
if (!Subtarget.hasSSE1()) break;

1
lib/Target/X86/X86WinAllocaExpander.cpp
View File

@ -225,6 +225,7 @@ void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) {
break;
// Fall through to make any remaining adjustment.
LLVM_FALLTHROUGH;
case Sub:
assert(Amount > 0);
if (Amount == SlotSize) {

2
lib/Target/XCore/XCoreAsmPrinter.cpp
View File

@ -140,7 +140,7 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
GV->hasCommonLinkage())
OutStreamer->EmitSymbolAttribute(GVSym, MCSA_Weak);
// FALL THROUGH
LLVM_FALLTHROUGH;
case GlobalValue::InternalLinkage:
case GlobalValue::PrivateLinkage:
break;

3
lib/Transforms/IPO/FunctionAttrs.cpp
View File

@ -775,7 +775,8 @@ static bool isFunctionMallocLike(Function *F, const SCCNodeSet &SCCNodes) {
break;
if (CS.getCalledFunction() && SCCNodes.count(CS.getCalledFunction()))
break;
} // fall-through
LLVM_FALLTHROUGH;
}
default:
return false; // Did not come from an allocation.
}

1
lib/Transforms/IPO/MergeFunctions.cpp
View File

@ -828,6 +828,7 @@ int FunctionComparator::cmpTypes(Type *TyL, Type *TyR) const {
default:
llvm_unreachable("Unknown type!");
// Fall through in Release mode.
LLVM_FALLTHROUGH;
case Type::IntegerTyID:
return cmpNumbers(cast<IntegerType>(TyL)->getBitWidth(),
cast<IntegerType>(TyR)->getBitWidth());

2
lib/Transforms/InstCombine/InstCombineCalls.cpp
View File

@ -1473,7 +1473,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
II->setArgOperand(1, LHS);
return II;
}
// fall through
LLVM_FALLTHROUGH;
case Intrinsic::usub_with_overflow:
case Intrinsic::ssub_with_overflow: {

15
lib/Transforms/InstCombine/InstCombineCompares.cpp
View File

@ -2715,8 +2715,10 @@ bool InstCombiner::OptimizeOverflowCheck(OverflowCheckFlavor OCF, Value *LHS,
if (OR == OverflowResult::AlwaysOverflows)
return SetResult(Builder->CreateAdd(LHS, RHS), Builder->getTrue(), true);
// Fall through uadd into sadd
LLVM_FALLTHROUGH;
}
// FALL THROUGH uadd into sadd
case OCF_SIGNED_ADD: {
// X + 0 -> {X, false}
if (match(RHS, m_Zero()))
@ -2756,7 +2758,8 @@ bool InstCombiner::OptimizeOverflowCheck(OverflowCheckFlavor OCF, Value *LHS,
true);
if (OR == OverflowResult::AlwaysOverflows)
return SetResult(Builder->CreateMul(LHS, RHS), Builder->getTrue(), true);
} // FALL THROUGH
LLVM_FALLTHROUGH;
}
case OCF_SIGNED_MUL:
// X * undef -> undef
if (isa<UndefValue>(RHS))
@ -3311,28 +3314,28 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
case ICmpInst::ICMP_UGT:
std::swap(Op0, Op1); // Change icmp ugt -> icmp ult
// FALL THROUGH
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_ULT:{ // icmp ult i1 A, B -> ~A & B
Value *Not = Builder->CreateNot(Op0, I.getName() + "tmp");
return BinaryOperator::CreateAnd(Not, Op1);
}
case ICmpInst::ICMP_SGT:
std::swap(Op0, Op1); // Change icmp sgt -> icmp slt
// FALL THROUGH
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_SLT: { // icmp slt i1 A, B -> A & ~B
Value *Not = Builder->CreateNot(Op1, I.getName() + "tmp");
return BinaryOperator::CreateAnd(Not, Op0);
}
case ICmpInst::ICMP_UGE:
std::swap(Op0, Op1); // Change icmp uge -> icmp ule
// FALL THROUGH
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_ULE: { // icmp ule i1 A, B -> ~A | B
Value *Not = Builder->CreateNot(Op0, I.getName() + "tmp");
return BinaryOperator::CreateOr(Not, Op1);
}
case ICmpInst::ICMP_SGE:
std::swap(Op0, Op1); // Change icmp sge -> icmp sle
// FALL THROUGH
LLVM_FALLTHROUGH;
case ICmpInst::ICMP_SLE: { // icmp sle i1 A, B -> A | ~B
Value *Not = Builder->CreateNot(Op1, I.getName() + "tmp");
return BinaryOperator::CreateOr(Not, Op0);

2
lib/Transforms/InstCombine/InstCombineShifts.cpp
View File

@ -457,9 +457,9 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
V1->getName()+".mask");
return BinaryOperator::Create(Op0BO->getOpcode(), YS, XM);
}
LLVM_FALLTHROUGH;
}
// FALL THROUGH.
case Instruction::Sub: {
// Turn ((X >> C) + Y) << C -> (X + (Y << C)) & (~0 << C)
if (isLeftShift && Op0BO->getOperand(0)->hasOneUse() &&

2
lib/Transforms/InstCombine/InstructionCombining.cpp
View File

@ -1983,8 +1983,8 @@ isAllocSiteRemovable(Instruction *AI, SmallVectorImpl<WeakVH> &Users,
MemIntrinsic *MI = cast<MemIntrinsic>(II);
if (MI->isVolatile() || MI->getRawDest() != PI)
return false;
LLVM_FALLTHROUGH;
}
// fall through
case Intrinsic::dbg_declare:
case Intrinsic::dbg_value:
case Intrinsic::invariant_start:

4
lib/Transforms/ObjCARC/PtrState.cpp
View File

@ -201,7 +201,7 @@ bool BottomUpPtrState::MatchWithRetain() {
// imprecise release, clear our reverse insertion points.
if (OldSeq != S_Use || IsTrackingImpreciseReleases())
ClearReverseInsertPts();
// FALL THROUGH
LLVM_FALLTHROUGH;
case S_CanRelease:
return true;
case S_None:
@ -332,7 +332,7 @@ bool TopDownPtrState::MatchWithRelease(ARCMDKindCache &Cache,
case S_CanRelease:
if (OldSeq == S_Retain || ReleaseMetadata != nullptr)
ClearReverseInsertPts();
// FALL THROUGH
LLVM_FALLTHROUGH;
case S_Use:
SetReleaseMetadata(ReleaseMetadata);
SetTailCallRelease(cast<CallInst>(Release)->isTailCall());

2
tools/llvm-config/llvm-config.cpp
View File

@ -599,7 +599,7 @@ int main(int argc, char **argv) {
}
errs()
<< "llvm-config: error: component libraries and shared library\n\n";
// fall through
LLVM_FALLTHROUGH;
case LinkModeStatic:
for (auto &Lib : MissingLibs)
errs() << "llvm-config: error: missing: " << Lib << "\n";

2
tools/llvm-mc/Disassembler.cpp
View File

@ -66,7 +66,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm,
SM.PrintMessage(SMLoc::getFromPointer(Bytes.second[Index]),
SourceMgr::DK_Warning,
"potentially undefined instruction encoding");
// Fall through
LLVM_FALLTHROUGH;
case MCDisassembler::Success:
Streamer.EmitInstruction(Inst, STI);

8
utils/TableGen/IntrinsicEmitter.cpp
View File

@ -287,10 +287,10 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes,
unsigned Tmp = 0;
switch (VT) {
default: break;
case MVT::iPTRAny: ++Tmp; // FALL THROUGH.
case MVT::vAny: ++Tmp; // FALL THROUGH.
case MVT::fAny: ++Tmp; // FALL THROUGH.
case MVT::iAny: ++Tmp; // FALL THROUGH.
case MVT::iPTRAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::vAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::fAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::iAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::Any: {
// If this is an "any" valuetype, then the type is the type of the next
// type in the list specified to getIntrinsic().