1
0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-11 15:08:16 +00:00

[mips] Implementation of dli.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL
    
Some small modifications to the original patch: we now error if
it's not possible to expand an instruction (mips-expansions-bad.s has some
examples). Added some comments to the expansions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211271 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matheus Almeida 2014-06-19 15:08:04 +00:00
parent 2710772655
commit 7e40983328
4 changed files with 313 additions and 8 deletions

@ -984,6 +984,7 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
case Mips::LoadImm32Reg:
case Mips::LoadAddr32Imm:
case Mips::LoadAddr32Reg:
case Mips::LoadImm64Reg:
return true;
default:
return false;
@ -997,6 +998,12 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
return true;
case Mips::LoadImm32Reg:
return expandLoadImm(Inst, IDLoc, Instructions);
case Mips::LoadImm64Reg:
if (!isGP64()) {
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
}
return expandLoadImm(Inst, IDLoc, Instructions);
case Mips::LoadAddr32Imm:
return expandLoadAddressImm(Inst, IDLoc, Instructions);
case Mips::LoadAddr32Reg:
@ -1004,6 +1011,30 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
}
}
namespace {
template <int Shift, bool PerformShift>
void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
MCInst tmpInst;
if (PerformShift) {
tmpInst.setOpcode(Mips::DSLL);
tmpInst.addOperand(MCOperand::CreateReg(RegNo));
tmpInst.addOperand(MCOperand::CreateReg(RegNo));
tmpInst.addOperand(MCOperand::CreateImm(16));
tmpInst.setLoc(IDLoc);
Instructions.push_back(tmpInst);
tmpInst.clear();
}
tmpInst.setOpcode(Mips::ORi);
tmpInst.addOperand(MCOperand::CreateReg(RegNo));
tmpInst.addOperand(MCOperand::CreateReg(RegNo));
tmpInst.addOperand(
MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)));
tmpInst.setLoc(IDLoc);
Instructions.push_back(tmpInst);
}
}
bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
MCInst tmpInst;
@ -1012,8 +1043,10 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
const MCOperand &RegOp = Inst.getOperand(0);
assert(RegOp.isReg() && "expected register operand kind");
int ImmValue = ImmOp.getImm();
int64_t ImmValue = ImmOp.getImm();
tmpInst.setLoc(IDLoc);
// FIXME: gas has a special case for values that are 000...1111, which
// becomes a li -1 and then a dsrl
if (0 <= ImmValue && ImmValue <= 65535) {
// For 0 <= j <= 65535.
// li d,j => ori d,$zero,j
@ -1030,21 +1063,71 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
Instructions.push_back(tmpInst);
} else {
// For any other value of j that is representable as a 32-bit integer.
} else if ((ImmValue & 0xffffffff) == ImmValue) {
// For any value of j that is representable as a 32-bit integer, create
// a sequence of:
// li d,j => lui d,hi16(j)
// ori d,d,lo16(j)
tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
Instructions.push_back(tmpInst);
tmpInst.clear();
tmpInst.setOpcode(Mips::ORi);
createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
} else if ((ImmValue & (0xffffLL << 48)) == 0) {
if (!isGP64()) {
Error (IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
}
// <------- lo32 ------>
// <------- hi32 ------>
// <- hi16 -> <- lo16 ->
// _________________________________
// | | | |
// | 16-bytes | 16-bytes | 16-bytes |
// |__________|__________|__________|
//
// For any value of j that is representable as a 48-bit integer, create
// a sequence of:
// li d,j => lui d,hi16(j)
// ori d,d,hi16(lo32(j))
// dsll d,d,16
// ori d,d,lo16(lo32(j))
tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
tmpInst.setLoc(IDLoc);
tmpInst.addOperand(
MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
Instructions.push_back(tmpInst);
createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
} else {
if (!isGP64()) {
Error (IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
}
// <------- hi32 ------> <------- lo32 ------>
// <- hi16 -> <- lo16 ->
// ___________________________________________
// | | | | |
// | 16-bytes | 16-bytes | 16-bytes | 16-bytes |
// |__________|__________|__________|__________|
//
// For any value of j that isn't representable as a 48-bit integer.
// li d,j => lui d,hi16(j)
// ori d,d,lo16(hi32(j))
// dsll d,d,16
// ori d,d,hi16(lo32(j))
// dsll d,d,16
// ori d,d,lo16(lo32(j))
tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
tmpInst.addOperand(
MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
Instructions.push_back(tmpInst);
createShiftOr<32, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
createShiftOr<16, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
}
return false;
}

@ -23,6 +23,8 @@ def uimm16_64 : Operand<i64> {
// Signed Operand
def simm10_64 : Operand<i64>;
def imm64: Operand<i64>;
// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
return getImm(N, (unsigned)N->getZExtValue() - 32);
@ -486,6 +488,11 @@ def : MipsInstAlias<"dsrl $rd, $rt, $rs",
(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
!strconcat(instr_asm, "\t$rt, $imm64")> ;
def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
/// Move between CPU and coprocessor registers
let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;

@ -0,0 +1,6 @@
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1
.text
li $5, 0x100000000 # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
dli $5, 1 # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled

@ -0,0 +1,209 @@
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
#
# The GNU assembler implements 'dli' and 'dla' variants on 'li' and 'la'
# supporting double-word lengths. Test that not only are they present, bu
# that they also seem to handle 64-bit values.
#
# XXXRW: Does using powers of ten make me a bad person?
#
# CHECK: ori $12, $zero, 1 # encoding: [0x01,0x00,0x0c,0x34]
# CHECK: ori $12, $zero, 10 # encoding: [0x0a,0x00,0x0c,0x34]
# CHECK: ori $12, $zero, 100 # encoding: [0x64,0x00,0x0c,0x34]
# CHECK: ori $12, $zero, 1000 # encoding: [0xe8,0x03,0x0c,0x34]
# CHECK: ori $12, $zero, 10000 # encoding: [0x10,0x27,0x0c,0x34]
# CHECK: lui $12, 1 # encoding: [0x01,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 34464 # encoding: [0xa0,0x86,0x8c,0x35]
# CHECK: lui $12, 15 # encoding: [0x0f,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 16960 # encoding: [0x40,0x42,0x8c,0x35]
# CHECK: lui $12, 152 # encoding: [0x98,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 38528 # encoding: [0x80,0x96,0x8c,0x35]
# CHECK: lui $12, 1525 # encoding: [0xf5,0x05,0x0c,0x3c]
# CHECK: ori $12, $12, 57600 # encoding: [0x00,0xe1,0x8c,0x35]
# CHECK: lui $12, 15258 # encoding: [0x9a,0x3b,0x0c,0x3c]
# CHECK: ori $12, $12, 51712 # encoding: [0x00,0xca,0x8c,0x35]
# CHECK: lui $12, 2 # encoding: [0x02,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 21515 # encoding: [0x0b,0x54,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 58368 # encoding: [0x00,0xe4,0x8c,0x35]
# CHECK: lui $12, 23 # encoding: [0x17,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 18550 # encoding: [0x76,0x48,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 59392 # encoding: [0x00,0xe8,0x8c,0x35]
# CHECK: lui $12, 232 # encoding: [0xe8,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 54437 # encoding: [0xa5,0xd4,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 4096 # encoding: [0x00,0x10,0x8c,0x35]
# CHECK: lui $12, 2328 # encoding: [0x18,0x09,0x0c,0x3c]
# CHECK: ori $12, $12, 20082 # encoding: [0x72,0x4e,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 40960 # encoding: [0x00,0xa0,0x8c,0x35]
# CHECK: lui $12, 23283 # encoding: [0xf3,0x5a,0x0c,0x3c]
# CHECK: ori $12, $12, 4218 # encoding: [0x7a,0x10,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 16384 # encoding: [0x00,0x40,0x8c,0x35]
# CHECK: lui $12, 3 # encoding: [0x03,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 36222 # encoding: [0x7e,0x8d,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 42182 # encoding: [0xc6,0xa4,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 32768 # encoding: [0x00,0x80,0x8c,0x35]
# CHECK: lui $12, 35 # encoding: [0x23,0x00,0x0c,0x3c]
# CHECK: ori $12, $12, 34546 # encoding: [0xf2,0x86,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 28609 # encoding: [0xc1,0x6f,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: lui $12, 355 # encoding: [0x63,0x01,0x0c,0x3c]
# CHECK: ori $12, $12, 17784 # encoding: [0x78,0x45,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 23946 # encoding: [0x8a,0x5d,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: lui $12, 3552 # encoding: [0xe0,0x0d,0x0c,0x3c]
# CHECK: ori $12, $12, 46771 # encoding: [0xb3,0xb6,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 42852 # encoding: [0x64,0xa7,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: lui $12, 35527 # encoding: [0xc7,0x8a,0x0c,0x3c]
# CHECK: ori $12, $12, 8964 # encoding: [0x04,0x23,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 35304 # encoding: [0xe8,0x89,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: addiu $12, $zero, -1 # encoding: [0xff,0xff,0x0c,0x24]
# CHECK: addiu $12, $zero, -10 # encoding: [0xf6,0xff,0x0c,0x24]
# CHECK: addiu $12, $zero, -100 # encoding: [0x9c,0xff,0x0c,0x24]
# CHECK: addiu $12, $zero, -1000 # encoding: [0x18,0xfc,0x0c,0x24]
# CHECK: addiu $12, $zero, -10000 # encoding: [0xf0,0xd8,0x0c,0x24]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 65534 # encoding: [0xfe,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 31072 # encoding: [0x60,0x79,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 65520 # encoding: [0xf0,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 48576 # encoding: [0xc0,0xbd,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 65383 # encoding: [0x67,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 27008 # encoding: [0x80,0x69,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 64010 # encoding: [0x0a,0xfa,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 7936 # encoding: [0x00,0x1f,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 50277 # encoding: [0x65,0xc4,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 13824 # encoding: [0x00,0x36,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65533 # encoding: [0xfd,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 44020 # encoding: [0xf4,0xab,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 7168 # encoding: [0x00,0x1c,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65512 # encoding: [0xe8,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 46985 # encoding: [0x89,0xb7,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 6144 # encoding: [0x00,0x18,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 65303 # encoding: [0x17,0xff,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 11098 # encoding: [0x5a,0x2b,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 61440 # encoding: [0x00,0xf0,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 63207 # encoding: [0xe7,0xf6,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 45453 # encoding: [0x8d,0xb1,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 24576 # encoding: [0x00,0x60,0x8c,0x35]
# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 42252 # encoding: [0x0c,0xa5,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 61317 # encoding: [0x85,0xef,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 49152 # encoding: [0x00,0xc0,0x8c,0x35]
# CHECK: lui $12, 65532 # encoding: [0xfc,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 29313 # encoding: [0x81,0x72,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 23353 # encoding: [0x39,0x5b,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 32768 # encoding: [0x00,0x80,0x8c,0x35]
# CHECK: lui $12, 65500 # encoding: [0xdc,0xff,0x0c,0x3c]
# CHECK: ori $12, $12, 30989 # encoding: [0x0d,0x79,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 36927 # encoding: [0x3f,0x90,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: lui $12, 65180 # encoding: [0x9c,0xfe,0x0c,0x3c]
# CHECK: ori $12, $12, 47751 # encoding: [0x87,0xba,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 41590 # encoding: [0x76,0xa2,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: lui $12, 61983 # encoding: [0x1f,0xf2,0x0c,0x3c]
# CHECK: ori $12, $12, 18764 # encoding: [0x4c,0x49,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 22684 # encoding: [0x9c,0x58,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
# CHECK: lui $12, 30008 # encoding: [0x38,0x75,0x0c,0x3c]
# CHECK: ori $12, $12, 56571 # encoding: [0xfb,0xdc,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 30232 # encoding: [0x18,0x76,0x8c,0x35]
# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00]
# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35]
dli $t0, 1
dli $t0, 10
dli $t0, 100
dli $t0, 1000
dli $t0, 10000
dli $t0, 100000
dli $t0, 1000000
dli $t0, 10000000
dli $t0, 100000000
dli $t0, 1000000000
dli $t0, 10000000000
dli $t0, 100000000000
dli $t0, 1000000000000
dli $t0, 10000000000000
dli $t0, 100000000000000
dli $t0, 1000000000000000
dli $t0, 10000000000000000
dli $t0, 100000000000000000
dli $t0, 1000000000000000000
dli $t0, 10000000000000000000
dli $t0, -1
dli $t0, -10
dli $t0, -100
dli $t0, -1000
dli $t0, -10000
dli $t0, -100000
dli $t0, -1000000
dli $t0, -10000000
dli $t0, -100000000
dli $t0, -1000000000
dli $t0, -10000000000
dli $t0, -100000000000
dli $t0, -1000000000000
dli $t0, -10000000000000
dli $t0, -100000000000000
dli $t0, -1000000000000000
dli $t0, -10000000000000000
dli $t0, -100000000000000000
dli $t0, -1000000000000000000
dli $t0, -10000000000000000000