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Fold some more [mem] op= val operators. This allows us to things like this

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several times in 256.bzip2:

        mov %EAX, DWORD PTR [%ESP + 204]
-       mov %EAX, DWORD PTR [%EAX]
-       or %EAX, 2097152
-       mov %ECX, DWORD PTR [%ESP + 204]
-       mov DWORD PTR [%ECX], %EAX
+       or DWORD PTR [%EAX], 2097152


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19492 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-12 01:28:00 +00:00
parent dbba22fa2a
commit 7ea64f5d12
1 changed files with 39 additions and 2 deletions
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41
lib/Target/X86/X86ISelPattern.cpp
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@ -2129,11 +2129,46 @@ void ISel::Select(SDOperand N) {
X86::ADD8mi, X86::ADD16mi, X86::ADD32mi, X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
X86::ADD8mr, X86::ADD16mr, X86::ADD32mr, 0, 0, X86::ADD8mr, X86::ADD16mr, X86::ADD32mr, 0, 0,
}; };
static const unsigned SUBTAB[] = {
X86::SUB8mi, X86::SUB16mi, X86::SUB32mi,
X86::SUB8mr, X86::SUB16mr, X86::SUB32mr, 0, 0,
};
static const unsigned ANDTAB[] = {
X86::AND8mi, X86::AND16mi, X86::AND32mi,
X86::AND8mr, X86::AND16mr, X86::AND32mr, 0, 0,
};
static const unsigned ORTAB[] = {
X86::OR8mi, X86::OR16mi, X86::OR32mi,
X86::OR8mr, X86::OR16mr, X86::OR32mr, 0, 0,
};
static const unsigned XORTAB[] = {
X86::XOR8mi, X86::XOR16mi, X86::XOR32mi,
X86::XOR8mr, X86::XOR16mr, X86::XOR32mr, 0, 0,
};
static const unsigned SHLTAB[] = {
X86::SHL8mi, X86::SHL16mi, X86::SHL32mi,
/*Have to put the reg in CL*/0, 0, 0, 0, 0,
};
static const unsigned SARTAB[] = {
X86::SAR8mi, X86::SAR16mi, X86::SAR32mi,
/*Have to put the reg in CL*/0, 0, 0, 0, 0,
};
static const unsigned SHRTAB[] = {
X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
/*Have to put the reg in CL*/0, 0, 0, 0, 0,
};
const unsigned *TabPtr = 0; const unsigned *TabPtr = 0;
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: break; default: std::cerr << "CANNOT [mem] op= val: "; Op.Val->dump(); std::cerr << "\n"; break;
case ISD::ADD: TabPtr = ADDTAB; break; case ISD::ADD: TabPtr = ADDTAB; break;
case ISD::SUB: TabPtr = SUBTAB; break;
case ISD::AND: TabPtr = ANDTAB; break;
case ISD:: OR: TabPtr = ORTAB; break;
case ISD::XOR: TabPtr = XORTAB; break;
case ISD::SHL: TabPtr = SHLTAB; break;
case ISD::SRA: TabPtr = SARTAB; break;
case ISD::SRL: TabPtr = SHRTAB; break;
} }
if (TabPtr) { if (TabPtr) {
@ -2166,7 +2201,9 @@ void ISel::Select(SDOperand N) {
// If we have [mem] = V op [mem], try to turn it into: // If we have [mem] = V op [mem], try to turn it into:
// [mem] = [mem] op V. // [mem] = [mem] op V.
if (Op1 == TheLoad && 1 /*iscommutative*/) if (Op1 == TheLoad && Op.getOpcode() != ISD::SUB &&
Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRA &&
Op.getOpcode() != ISD::SRL)
std::swap(Op0, Op1); std::swap(Op0, Op1);
if (Op0 == TheLoad) { if (Op0 == TheLoad) {