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Silence a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1111,7 +1111,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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// Form the pair instruction instead.
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unsigned EvenReg = 0, OddReg = 0;
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unsigned BaseReg = 0, OffReg = 0, PredReg = 0;
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ARMCC::CondCodes Pred;
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ARMCC::CondCodes Pred = ARMCC::AL;
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DebugLoc dl;
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for (unsigned i = 0; i != NumMove; ++i) {
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MachineInstr *Op = Ops.back();
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