From 7fd9d5636a63de6feab7a9ad8a9d0df265f2c1cb Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Fri, 12 Sep 2014 13:51:58 +0000 Subject: [PATCH] [mips][microMIPS] Implement BGEZALS and BLTZALS instructions Differential Revision: http://reviews.llvm.org/D5004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217678 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 2 ++ lib/Target/Mips/MicroMipsInstrInfo.td | 11 +++++++++++ test/MC/Mips/micromips-branch-instructions.s | 10 ++++++++++ 3 files changed, 23 insertions(+) diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 1a5aed47b32..5500a434c36 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -985,6 +985,8 @@ static bool hasShortDelaySlot(unsigned Opcode) { switch (Opcode) { case Mips::JALS_MM: case Mips::JALRS_MM: + case Mips::BGEZALS_MM: + case Mips::BLTZALS_MM: return true; default: return false; diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index dbbf1602919..41654ac1def 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -115,6 +115,11 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in { class JumpLinkRegMM: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), [], IIBranch, FrmR>; + + class BranchCompareToZeroLinkMM : + InstSE<(outs), (ins RO:$rs, opnd:$offset), + !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; } def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; @@ -298,6 +303,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>, BGEZAL_FM_MM<0x01>; + /// Branch Instructions - Short Delay Slot + def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm, + GPR32Opnd>, BGEZAL_FM_MM<0x13>; + def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, + GPR32Opnd>, BGEZAL_FM_MM<0x11>; + /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; diff --git a/test/MC/Mips/micromips-branch-instructions.s b/test/MC/Mips/micromips-branch-instructions.s index 84df2a17c83..cf0aab7873d 100644 --- a/test/MC/Mips/micromips-branch-instructions.s +++ b/test/MC/Mips/micromips-branch-instructions.s @@ -29,6 +29,10 @@ # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: bltz $6, 1332 # encoding: [0x06,0x40,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: bgezals $6, 1332 # encoding: [0x66,0x42,0x9a,0x02] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: bltzals $6, 1332 # encoding: [0x26,0x42,0x9a,0x02] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -52,6 +56,10 @@ # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: bltz $6, 1332 # encoding: [0x40,0x06,0x02,0x9a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: bgezals $6, 1332 # encoding: [0x42,0x66,0x02,0x9a] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: bltzals $6, 1332 # encoding: [0x42,0x26,0x02,0x9a] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] b 1332 beq $9,$6,1332 @@ -63,3 +71,5 @@ bne $9,$6,1332 bal 1332 bltz $6,1332 + bgezals $6,1332 + bltzals $6,1332