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Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-07-28 18:59:19 +00:00
parent eb6d794834
commit 7fe1b96ef0
1 changed files with 34 additions and 49 deletions
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83
lib/Target/X86/X86InstrSSE.td
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@ -1757,37 +1757,34 @@ def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
// Convert packed single/double fp to doubleword
def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtps2dq\t{$src, $dst|$dst, $src}", [],
"cvtps2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
IIC_SSE_CVT_PS_RR>, VEX;
def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"cvtps2dq\t{$src, $dst|$dst, $src}", [],
"cvtps2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
IIC_SSE_CVT_PS_RM>, VEX;
def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
"cvtps2dq\t{$src, $dst|$dst, $src}", [],
"cvtps2dq\t{$src, $dst|$dst, $src}",
[(set VR256:$dst,
(int_x86_avx_cvt_ps2dq_256 VR256:$src))],
IIC_SSE_CVT_PS_RR>, VEX;
def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
"cvtps2dq\t{$src, $dst|$dst, $src}", [],
"cvtps2dq\t{$src, $dst|$dst, $src}",
[(set VR256:$dst,
(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
IIC_SSE_CVT_PS_RM>, VEX;
def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtps2dq\t{$src, $dst|$dst, $src}", [],
"cvtps2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
IIC_SSE_CVT_PS_RR>;
def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"cvtps2dq\t{$src, $dst|$dst, $src}", [],
"cvtps2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
IIC_SSE_CVT_PS_RM>;
let Predicates = [HasAVX] in {
def : Pat<(int_x86_sse2_cvtps2dq VR128:$src),
(VCVTPS2DQrr VR128:$src)>;
def : Pat<(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)),
(VCVTPS2DQrm addr:$src)>;
}
let Predicates = [HasSSE2] in {
def : Pat<(int_x86_sse2_cvtps2dq VR128:$src),
(CVTPS2DQrr VR128:$src)>;
def : Pat<(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)),
(CVTPS2DQrm addr:$src)>;
}
// Convert Packed Double FP to Packed DW Integers
let Predicates = [HasAVX] in {
@ -1795,44 +1792,42 @@ let Predicates = [HasAVX] in {
// register, but the same isn't true when using memory operands instead.
// Provide other assembly rr and rm forms to address this explicitly.
def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
"vcvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
VEX;
// XMM only
def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
(VCVTPD2DQrr VR128:$dst, VR128:$src)>;
def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
// YMM only
def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
"vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
"vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX;
def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
"vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
"vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
VEX, VEX_L;
def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
(VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
}
def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}", [],
"cvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
IIC_SSE_CVT_PD_RM>;
def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}", [],
"cvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
IIC_SSE_CVT_PD_RR>;
let Predicates = [HasAVX] in {
def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
(VCVTPD2DQrr VR128:$src)>;
def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
(VCVTPD2DQXrm addr:$src)>;
}
let Predicates = [HasSSE2] in {
def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
(CVTPD2DQrr VR128:$src)>;
def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
(CVTPD2DQrm addr:$src)>;
}
// Convert with truncation packed single/double fp to doubleword
// SSE2 packed instructions with XS prefix
def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
@ -2028,11 +2023,6 @@ let Predicates = [HasAVX] in {
def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
(VCVTDQ2PDYrm addr:$src)>;
def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
(VCVTPD2DQYrr VR256:$src)>;
def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
(VCVTPD2DQYrm addr:$src)>;
def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
(VCVTDQ2PDYrr VR128:$src)>;
def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
@ -2100,11 +2090,6 @@ let Predicates = [HasAVX] in {
def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
(VCVTPD2PSYrm addr:$src)>;
def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
(VCVTPS2DQYrr VR256:$src)>;
def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
(VCVTPS2DQYrm addr:$src)>;
def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
(VCVTPS2PDYrr VR128:$src)>;
def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),