RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-25 13:35:10 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-07-11 00:48:23 +00:00
parent b64ab8769e
commit 804e067042
3 changed files with 99 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -19,7 +19,8 @@
using namespace llvm;
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm) {}
: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm),
RI(*TM.getSubtargetImpl()) {}
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.

153
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -15,6 +15,7 @@
#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCRegisterInfo.h"
#include "PPCSubtarget.h"
#include "llvm/Constants.h"
#include "llvm/Type.h"
#include "llvm/CodeGen/ValueTypes.h"
@ -78,8 +79,9 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
}
}
PPCRegisterInfo::PPCRegisterInfo()
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
Subtarget(ST) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
@ -207,70 +209,103 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
PPC::R1, PPC::R13,
PPC::R14, PPC::R15,
PPC::R16, PPC::R17,
PPC::R18, PPC::R19,
PPC::R20, PPC::R21,
PPC::R22, PPC::R23,
PPC::R24, PPC::R25,
PPC::R26, PPC::R27,
PPC::R28, PPC::R29,
PPC::R30, PPC::R31,
PPC::F14, PPC::F15,
PPC::F16, PPC::F17,
PPC::F18, PPC::F19,
PPC::F20, PPC::F21,
PPC::F22, PPC::F23,
PPC::F24, PPC::F25,
PPC::F26, PPC::F27,
PPC::F28, PPC::F29,
// 32-bit Darwin calling convention.
static const unsigned Darwin32_CalleeSaveRegs[] = {
PPC::R1 , PPC::R13, PPC::R14, PPC::R15,
PPC::R16, PPC::R17, PPC::R18, PPC::R19,
PPC::R20, PPC::R21, PPC::R22, PPC::R23,
PPC::R24, PPC::R25, PPC::R26, PPC::R27,
PPC::R28, PPC::R29, PPC::R30, PPC::R31,
PPC::F14, PPC::F15, PPC::F16, PPC::F17,
PPC::F18, PPC::F19, PPC::F20, PPC::F21,
PPC::F22, PPC::F23, PPC::F24, PPC::F25,
PPC::F26, PPC::F27, PPC::F28, PPC::F29,
PPC::F30, PPC::F31,
PPC::CR2, PPC::CR3,
PPC::CR4, PPC::V20,
PPC::V21, PPC::V22,
PPC::V23, PPC::V24,
PPC::V25, PPC::V26,
PPC::V27, PPC::V28,
PPC::V29, PPC::V30,
PPC::V31, PPC::LR, 0
PPC::CR2, PPC::CR3, PPC::CR4,
PPC::V20, PPC::V21, PPC::V22, PPC::V23,
PPC::V24, PPC::V25, PPC::V26, PPC::V27,
PPC::V28, PPC::V29, PPC::V30, PPC::V31,
PPC::LR, 0
};
return CalleeSaveRegs;
// 64-bit Darwin calling convention.
static const unsigned Darwin64_CalleeSaveRegs[] = {
PPC::X1 , PPC::X13, PPC::X14, PPC::X15,
PPC::X16, PPC::X17, PPC::X18, PPC::X19,
PPC::X20, PPC::X21, PPC::X22, PPC::X23,
PPC::X24, PPC::X25, PPC::X26, PPC::X27,
PPC::X28, PPC::X29, PPC::X30, PPC::X31,
PPC::F14, PPC::F15, PPC::F16, PPC::F17,
PPC::F18, PPC::F19, PPC::F20, PPC::F21,
PPC::F22, PPC::F23, PPC::F24, PPC::F25,
PPC::F26, PPC::F27, PPC::F28, PPC::F29,
PPC::F30, PPC::F31,
PPC::CR2, PPC::CR3, PPC::CR4,
PPC::V20, PPC::V21, PPC::V22, PPC::V23,
PPC::V24, PPC::V25, PPC::V26, PPC::V27,
PPC::V28, PPC::V29, PPC::V30, PPC::V31,
PPC::LR, 0
};
return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
Darwin32_CalleeSaveRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::CRRCRegClass, &PPC::CRRCRegClass,
&PPC::CRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
// 32-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::GPRCRegClass, 0
};
return CalleeSaveRegClasses;
// 64-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
&PPC::GPRCRegClass, 0
};
return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
Darwin32_CalleeSaveRegClasses;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into

5
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -19,13 +19,14 @@
#include <map>
namespace llvm {
class PPCSubtarget;
class Type;
class PPCRegisterInfo : public PPCGenRegisterInfo {
std::map<unsigned, unsigned> ImmToIdxMap;
const PPCSubtarget &Subtarget;
public:
PPCRegisterInfo();
PPCRegisterInfo(const PPCSubtarget &SubTarget);
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// PPC::F14, return the number that it corresponds to (e.g. 14).