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[SelectionDAG] Scalar shift amounts may require legalization

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The shift amount may be too small to cope with promoted left hand side,
make sure to promote it as well.

This fixes PR23664.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238503 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2015-05-28 21:29:59 +00:00
parent cb95e9ef45
commit 81f64c04d7
1 changed files with 6 additions and 3 deletions
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9
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -604,7 +604,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
SDValue Res = GetPromotedInteger(N->getOperand(0));
SDValue Amt = N->getOperand(1);
Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
if (!TLI.isTypeLegal(Amt.getValueType()))
Amt = ZExtPromotedInteger(N->getOperand(1));
return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
}
@ -628,7 +629,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
// The input value must be properly sign extended.
SDValue Res = SExtPromotedInteger(N->getOperand(0));
SDValue Amt = N->getOperand(1);
Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
if (!TLI.isTypeLegal(Amt.getValueType()))
Amt = ZExtPromotedInteger(N->getOperand(1));
return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
}
@ -636,7 +638,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
// The input value must be properly zero extended.
SDValue Res = ZExtPromotedInteger(N->getOperand(0));
SDValue Amt = N->getOperand(1);
Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
if (!TLI.isTypeLegal(Amt.getValueType()))
Amt = ZExtPromotedInteger(N->getOperand(1));
return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
}