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Set hasSideEffects=0 for PHI and fix affected passes

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Previously, hasSideEffects was ? for TargetOpcode::PHI and would be inferred 
as 1. D37065 sets the previously inferred properties explicitly. This patch sets 
hasSideEffects=0 for PHI, as it is for G_PHI. MachineInstr::isSafeToMove has 
been updated so it still returns false for PHI.

Additionally, HexagonBitSimplify relied on a PHI node having the 
hasUnmodeledSideEffects property. This patch fixes that assumption.

Differential Revision: https://reviews.llvm.org/D37097


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Bradbury 2017-11-08 20:19:16 +00:00
parent fb2f519709
commit 81fd138d35
3 changed files with 4 additions and 5 deletions
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2
include/llvm/Target/Target.td
View File

@ -893,7 +893,7 @@ def PHI : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
let AsmString = "PHINODE";
let hasSideEffects = 1;
let hasSideEffects = 0;
}
def INLINEASM : Instruction {
let OutOperandList = (outs);

2
lib/CodeGen/MachineInstr.cpp
View File

@ -1686,7 +1686,7 @@ bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
// Treat volatile loads as stores. This is not strictly necessary for
// volatiles, but it is required for atomic loads. It is not allowed to move
// a load across an atomic load with Ordering > Monotonic.
if (mayStore() || isCall() ||
if (mayStore() || isCall() || isPHI() ||
(mayLoad() && hasOrderedMemoryRef())) {
SawStore = true;
return false;

5
lib/Target/Hexagon/HexagonBitSimplify.cpp
View File

@ -1315,7 +1315,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
if (MI->getOpcode() == TargetOpcode::COPY)
continue;
if (MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
if (MI->isPHI() || MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
continue;
unsigned NumD = MI->getDesc().getNumDefs();
if (NumD != 1)
@ -1325,8 +1325,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
if (!BT.has(RD.Reg))
continue;
const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
auto At = MachineBasicBlock::iterator(MI);
// Find a source operand that is equal to the result.
for (auto &Op : MI->uses()) {