mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-28 07:05:03 +00:00
Tidy up. Simplify logic. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
d22170e16a
commit
8209968306
@ -92,26 +92,26 @@ static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
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MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
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switch (Kind) {
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default: assert(0 && "Invalid kind!");
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case MCSymbolRefExpr::VK_None: break;
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case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break;
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case MCSymbolRefExpr::VK_Mips_GOT16: OS << "%got("; break;
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case MCSymbolRefExpr::VK_Mips_GOT: OS << "%got("; break;
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case MCSymbolRefExpr::VK_Mips_ABS_HI: OS << "%hi("; break;
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case MCSymbolRefExpr::VK_Mips_ABS_LO: OS << "%lo("; break;
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case MCSymbolRefExpr::VK_Mips_TLSGD: OS << "%tlsgd("; break;
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case MCSymbolRefExpr::VK_Mips_TLSLDM: OS << "%tlsldm("; break;
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case MCSymbolRefExpr::VK_Mips_DTPREL_HI:OS << "%dtprel_hi("; break;
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case MCSymbolRefExpr::VK_Mips_DTPREL_LO:OS << "%dtprel_lo("; break;
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case MCSymbolRefExpr::VK_Mips_GOTTPREL: OS << "%gottprel("; break;
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case MCSymbolRefExpr::VK_Mips_TPREL_HI: OS << "%tprel_hi("; break;
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case MCSymbolRefExpr::VK_Mips_TPREL_LO: OS << "%tprel_lo("; break;
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case MCSymbolRefExpr::VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break;
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case MCSymbolRefExpr::VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_DISP: OS << "%got_disp("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_PAGE: OS << "%got_page("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_OFST: OS << "%got_ofst("; break;
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default: assert(0 && "Invalid kind!");
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case MCSymbolRefExpr::VK_None: break;
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case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break;
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case MCSymbolRefExpr::VK_Mips_GOT16: OS << "%got("; break;
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case MCSymbolRefExpr::VK_Mips_GOT: OS << "%got("; break;
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case MCSymbolRefExpr::VK_Mips_ABS_HI: OS << "%hi("; break;
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case MCSymbolRefExpr::VK_Mips_ABS_LO: OS << "%lo("; break;
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case MCSymbolRefExpr::VK_Mips_TLSGD: OS << "%tlsgd("; break;
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case MCSymbolRefExpr::VK_Mips_TLSLDM: OS << "%tlsldm("; break;
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case MCSymbolRefExpr::VK_Mips_DTPREL_HI: OS << "%dtprel_hi("; break;
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case MCSymbolRefExpr::VK_Mips_DTPREL_LO: OS << "%dtprel_lo("; break;
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case MCSymbolRefExpr::VK_Mips_GOTTPREL: OS << "%gottprel("; break;
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case MCSymbolRefExpr::VK_Mips_TPREL_HI: OS << "%tprel_hi("; break;
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case MCSymbolRefExpr::VK_Mips_TPREL_LO: OS << "%tprel_lo("; break;
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case MCSymbolRefExpr::VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break;
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case MCSymbolRefExpr::VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_DISP: OS << "%got_disp("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_PAGE: OS << "%got_page("; break;
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case MCSymbolRefExpr::VK_Mips_GOT_OFST: OS << "%got_ofst("; break;
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}
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OS << SRE->getSymbol();
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@ -142,7 +142,8 @@ extern "C" void LLVMInitializeMipsTargetMC() {
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TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, createMipsAsmBackend);
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TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget, createMipsMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget, createMipsMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget,
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createMipsMCCodeEmitter);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
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@ -459,7 +459,8 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
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// Tell the assembler which ABI we are using
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if (OutStreamer.hasRawTextSupport())
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OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
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OutStreamer.EmitRawText("\t.section .mdebug." +
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Twine(getCurrentABIString()));
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// TODO: handle O64 ABI
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if (OutStreamer.hasRawTextSupport()) {
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@ -107,7 +107,8 @@ class MipsCodeEmitter : public MachineFunctionPass {
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unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getBranchTargetOpValue(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
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@ -119,7 +120,7 @@ class MipsCodeEmitter : public MachineFunctionPass {
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int emitUSH(const MachineInstr &MI);
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void emitGlobalAddressUnaligned(const GlobalValue *GV, unsigned Reloc,
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int Offset) const;
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int Offset) const;
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};
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}
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@ -105,8 +105,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) {
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MBB.splice(llvm::next(I), &MBB, D);
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++UsefulSlots;
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}
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else
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} else
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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// Record the filler instruction that filled the delay slot.
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@ -167,8 +166,7 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB,
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}
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bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad,
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bool &sawStore,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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if (candidate->isImplicitDef() || candidate->isKill())
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@ -294,7 +294,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
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if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Mips::ZERO, MVT::i32);
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Mips::ZERO, MVT::i32);
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return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
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Zero);
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}
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@ -315,10 +315,12 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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DestReg = Mips::V1_64;
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}
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SDNode *Rdhwr = CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
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Node->getValueType(0), CurDAG->getRegister(SrcReg, PtrVT));
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SDNode *Rdhwr =
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CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
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Node->getValueType(0),
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CurDAG->getRegister(SrcReg, PtrVT));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
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SDValue(Rdhwr, 0));
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SDValue(Rdhwr, 0));
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SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
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ReplaceUses(SDValue(Node, 0), ResNode);
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return ResNode.getNode();
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@ -297,8 +297,7 @@ static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
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// create MipsMAdd(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
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SDValue MAdd = CurDAG->getNode(MultOpc, dl,
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MVT::Glue,
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SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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ADDCNode->getOperand(1),// Lo0
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@ -371,8 +370,7 @@ static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
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// create MipsSub(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
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SDValue MSub = CurDAG->getNode(MultOpc, dl,
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MVT::Glue,
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SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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SUBCNode->getOperand(0),// Lo0
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@ -490,11 +488,10 @@ static bool InvertFPCondCode(Mips::CondCode CC) {
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if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
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return false;
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if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
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return true;
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assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
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"Illegal Condition Code");
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assert(false && "Illegal Condition Code");
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return false;
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return true;
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}
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// Creates and returns an FPCmp node from a setcc node.
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@ -584,8 +581,7 @@ static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
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return SDValue();
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return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
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ShiftRight.getOperand(0),
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DAG.getConstant(Pos, MVT::i32),
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ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
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DAG.getConstant(SMSize, MVT::i32));
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}
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@ -638,11 +634,9 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
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if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
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return SDValue();
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return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy,
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Shl.getOperand(0),
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return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
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DAG.getConstant(SMPos0, MVT::i32),
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DAG.getConstant(SMSize0, MVT::i32),
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And0.getOperand(0));
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DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
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}
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SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
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@ -713,10 +707,10 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
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if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
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return Mips::BRANCH_T;
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if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
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return Mips::BRANCH_F;
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assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
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"Invalid CondCode.");
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return Mips::BRANCH_INVALID;
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return Mips::BRANCH_F;
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}
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/*
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@ -1049,8 +1043,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(loopMBB);
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@ -1082,7 +1075,6 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
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BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
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// atomic.load.binop
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// loopMBB:
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// ll oldval,0(alignedaddr)
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@ -1201,8 +1193,7 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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// thisMBB:
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@ -1290,8 +1281,7 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(loop1MBB);
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@ -1493,9 +1483,8 @@ SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
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(HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
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SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
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GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GA);
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SDValue ResNode = DAG.getLoad(ValTy, dl,
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DAG.getEntryNode(), GA, MachinePointerInfo(),
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false, false, false, 0);
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SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
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MachinePointerInfo(), false, false, false, 0);
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// On functions and global targets not internal linked only
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// a load from got/GP is necessary for PIC to work.
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if (!HasGotOfst)
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@ -1515,10 +1504,8 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
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// %hi/%lo relocation
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SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
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MipsII::MO_ABS_HI);
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SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
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MipsII::MO_ABS_LO);
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SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
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SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
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SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
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SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
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return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
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@ -1530,8 +1517,7 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
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SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
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BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, BAGOTOffset);
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SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
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SDValue Load = DAG.getLoad(ValTy, dl,
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DAG.getEntryNode(), BAGOTOffset,
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SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
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MachinePointerInfo(), false, false, false, 0);
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SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
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return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
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@ -1672,9 +1658,9 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
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SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
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N->getOffset(), GOTFlag);
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CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, CP);
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SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(),
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CP, MachinePointerInfo::getConstantPool(),
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false, false, false, 0);
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SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
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MachinePointerInfo::getConstantPool(), false,
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false, false, 0);
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SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
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N->getOffset(), OFSTFlag);
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SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
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@ -1696,8 +1682,7 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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// memory location argument.
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
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MachinePointerInfo(SV),
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false, false, 0);
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MachinePointerInfo(SV), false, false, 0);
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}
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// Called if the size of integer registers is large enough to hold the whole
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@ -1750,16 +1735,16 @@ LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) {
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return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
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}
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SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
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const {
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SDValue
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MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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EVT Ty = Op.getValueType();
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assert(Ty == MVT::f32 || Ty == MVT::f64);
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if (Ty == MVT::f32 || HasMips64)
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return LowerFCOPYSIGNLargeIntReg(Op, DAG);
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else
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return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle());
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return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle());
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}
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SDValue MipsTargetLowering::
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@ -1778,8 +1763,8 @@ LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
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}
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// TODO: set SType according to the desired memory barrier behavior.
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SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op,
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SelectionDAG& DAG) const {
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SDValue
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MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
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unsigned SType = 0;
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DebugLoc dl = Op.getDebugLoc();
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return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
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@ -2007,9 +1992,8 @@ WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
|
||||
SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
|
||||
DAG.getConstant(Offset, MVT::i32));
|
||||
SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
|
||||
MachinePointerInfo(),
|
||||
false, false, false, std::min(ByValAlign,
|
||||
(unsigned )4));
|
||||
MachinePointerInfo(), false, false, false,
|
||||
std::min(ByValAlign, (unsigned )4));
|
||||
MemOpChains.push_back(LoadVal.getValue(1));
|
||||
unsigned DstReg = O32IntRegs[LocMemOffset / 4];
|
||||
RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
|
||||
@ -2190,7 +2174,7 @@ MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
|
||||
// Analyze operands of the call, assigning locations to each operand.
|
||||
SmallVector<CCValAssign, 16> ArgLocs;
|
||||
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
||||
getTargetMachine(), ArgLocs, *DAG.getContext());
|
||||
getTargetMachine(), ArgLocs, *DAG.getContext());
|
||||
|
||||
if (IsO32)
|
||||
CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
|
||||
@ -2323,8 +2307,7 @@ MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
|
||||
// emit ISD::STORE whichs stores the
|
||||
// parameter value to a stack Location
|
||||
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
MachinePointerInfo(), false, false, 0));
|
||||
}
|
||||
|
||||
// Extend range of indices of frame objects for outgoing arguments that were
|
||||
@ -2376,8 +2359,8 @@ MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
|
||||
OpFlag = MipsII::MO_NO_FLAG;
|
||||
else // O32 & PIC
|
||||
OpFlag = MipsII::MO_GOT_CALL;
|
||||
Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
|
||||
getPointerTy(), OpFlag);
|
||||
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
|
||||
OpFlag);
|
||||
GlobalOrExternal = true;
|
||||
}
|
||||
|
||||
@ -2552,8 +2535,7 @@ SDValue
|
||||
MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
||||
CallingConv::ID CallConv,
|
||||
bool isVarArg,
|
||||
const SmallVectorImpl<ISD::InputArg>
|
||||
&Ins,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
DebugLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals)
|
||||
const {
|
||||
@ -2569,7 +2551,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
||||
// Assign locations to all of the incoming arguments.
|
||||
SmallVector<CCValAssign, 16> ArgLocs;
|
||||
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
||||
getTargetMachine(), ArgLocs, *DAG.getContext());
|
||||
getTargetMachine(), ArgLocs, *DAG.getContext());
|
||||
|
||||
if (IsO32)
|
||||
CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
|
||||
@ -2719,8 +2701,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
||||
LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
|
||||
SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
|
||||
OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
|
||||
MachinePointerInfo(),
|
||||
false, false, 0));
|
||||
MachinePointerInfo(), false, false, 0));
|
||||
}
|
||||
}
|
||||
|
||||
@ -2774,8 +2755,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
|
||||
CCValAssign &VA = RVLocs[i];
|
||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||
|
||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||
OutVals[i], Flag);
|
||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
|
||||
|
||||
// guarantee that all emitted copies are
|
||||
// stuck together, avoiding something bad
|
||||
|
||||
@ -246,21 +246,21 @@ static unsigned GetAnalyzableBrOpc(unsigned Opc) {
|
||||
unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
|
||||
{
|
||||
switch (Opc) {
|
||||
default: llvm_unreachable("Illegal opcode!");
|
||||
case Mips::BEQ : return Mips::BNE;
|
||||
case Mips::BNE : return Mips::BEQ;
|
||||
case Mips::BGTZ : return Mips::BLEZ;
|
||||
case Mips::BGEZ : return Mips::BLTZ;
|
||||
case Mips::BLTZ : return Mips::BGEZ;
|
||||
case Mips::BLEZ : return Mips::BGTZ;
|
||||
case Mips::BEQ64 : return Mips::BNE64;
|
||||
case Mips::BNE64 : return Mips::BEQ64;
|
||||
case Mips::BGTZ64 : return Mips::BLEZ64;
|
||||
case Mips::BGEZ64 : return Mips::BLTZ64;
|
||||
case Mips::BLTZ64 : return Mips::BGEZ64;
|
||||
case Mips::BLEZ64 : return Mips::BGTZ64;
|
||||
case Mips::BC1T : return Mips::BC1F;
|
||||
case Mips::BC1F : return Mips::BC1T;
|
||||
default: llvm_unreachable("Illegal opcode!");
|
||||
case Mips::BEQ: return Mips::BNE;
|
||||
case Mips::BNE: return Mips::BEQ;
|
||||
case Mips::BGTZ: return Mips::BLEZ;
|
||||
case Mips::BGEZ: return Mips::BLTZ;
|
||||
case Mips::BLTZ: return Mips::BGEZ;
|
||||
case Mips::BLEZ: return Mips::BGTZ;
|
||||
case Mips::BEQ64: return Mips::BNE64;
|
||||
case Mips::BNE64: return Mips::BEQ64;
|
||||
case Mips::BGTZ64: return Mips::BLEZ64;
|
||||
case Mips::BGEZ64: return Mips::BLTZ64;
|
||||
case Mips::BLTZ64: return Mips::BGEZ64;
|
||||
case Mips::BLEZ64: return Mips::BGTZ64;
|
||||
case Mips::BC1T: return Mips::BC1F;
|
||||
case Mips::BC1F: return Mips::BC1T;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -229,24 +229,26 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pattern fragment for load/store
|
||||
//===----------------------------------------------------------------------===//
|
||||
class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
|
||||
class UnalignedLoad<PatFrag Node> :
|
||||
PatFrag<(ops node:$ptr), (Node node:$ptr), [{
|
||||
LoadSDNode *LD = cast<LoadSDNode>(N);
|
||||
return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
|
||||
}]>;
|
||||
|
||||
class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
|
||||
class AlignedLoad<PatFrag Node> :
|
||||
PatFrag<(ops node:$ptr), (Node node:$ptr), [{
|
||||
LoadSDNode *LD = cast<LoadSDNode>(N);
|
||||
return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
|
||||
}]>;
|
||||
|
||||
class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
|
||||
(Node node:$val, node:$ptr), [{
|
||||
class UnalignedStore<PatFrag Node> :
|
||||
PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
|
||||
StoreSDNode *SD = cast<StoreSDNode>(N);
|
||||
return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
|
||||
}]>;
|
||||
|
||||
class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
|
||||
(Node node:$val, node:$ptr), [{
|
||||
class AlignedStore<PatFrag Node> :
|
||||
PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
|
||||
StoreSDNode *SD = cast<StoreSDNode>(N);
|
||||
return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
|
||||
}]>;
|
||||
|
||||
@ -37,26 +37,26 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
|
||||
const MCSymbol *Symbol;
|
||||
|
||||
switch(MO.getTargetFlags()) {
|
||||
default: assert(0 && "Invalid target flag!");
|
||||
case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
|
||||
case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
|
||||
case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
|
||||
case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break;
|
||||
case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break;
|
||||
case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break;
|
||||
case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break;
|
||||
case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break;
|
||||
case MipsII::MO_TLSLDM: Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break;
|
||||
case MipsII::MO_DTPREL_HI:Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break;
|
||||
case MipsII::MO_DTPREL_LO:Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break;
|
||||
case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break;
|
||||
case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break;
|
||||
case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break;
|
||||
case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break;
|
||||
case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break;
|
||||
case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
|
||||
case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
|
||||
case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
|
||||
default: assert(0 && "Invalid target flag!");
|
||||
case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
|
||||
case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
|
||||
case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
|
||||
case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break;
|
||||
case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break;
|
||||
case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break;
|
||||
case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break;
|
||||
case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break;
|
||||
case MipsII::MO_TLSLDM: Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break;
|
||||
case MipsII::MO_DTPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break;
|
||||
case MipsII::MO_DTPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break;
|
||||
case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break;
|
||||
case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break;
|
||||
case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break;
|
||||
case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break;
|
||||
case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break;
|
||||
case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
|
||||
case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
|
||||
case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
|
||||
}
|
||||
|
||||
switch (MOTy) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user