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Tidy up. Simplify logic. No functional change intended.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-12-19 19:52:25 +00:00
parent d22170e16a
commit 8209968306
10 changed files with 117 additions and 132 deletions
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3
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
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@ -142,7 +142,8 @@ extern "C" void LLVMInitializeMipsTargetMC() {
TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, createMipsAsmBackend); TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, createMipsAsmBackend);
TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget, createMipsMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget, createMipsMCCodeEmitter);
TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget, createMipsMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget,
createMipsMCCodeEmitter);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,

3
lib/Target/Mips/MipsAsmPrinter.cpp
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@ -459,7 +459,8 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// Tell the assembler which ABI we are using // Tell the assembler which ABI we are using
if (OutStreamer.hasRawTextSupport()) if (OutStreamer.hasRawTextSupport())
OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString())); OutStreamer.EmitRawText("\t.section .mdebug." +
Twine(getCurrentABIString()));
// TODO: handle O64 ABI // TODO: handle O64 ABI
if (OutStreamer.hasRawTextSupport()) { if (OutStreamer.hasRawTextSupport()) {

3
lib/Target/Mips/MipsCodeEmitter.cpp
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@ -107,7 +107,8 @@ class MipsCodeEmitter : public MachineFunctionPass {
unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const; unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const; unsigned getBranchTargetOpValue(const MachineInstr &MI,
unsigned OpNo) const;
unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;

6
lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -105,8 +105,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB) {
if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) { if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) {
MBB.splice(llvm::next(I), &MBB, D); MBB.splice(llvm::next(I), &MBB, D);
++UsefulSlots; ++UsefulSlots;
} } else
else
BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
// Record the filler instruction that filled the delay slot. // Record the filler instruction that filled the delay slot.
@ -167,8 +166,7 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB,
} }
bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate, bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
bool &sawLoad, bool &sawLoad, bool &sawStore,
bool &sawStore,
SmallSet<unsigned, 32> &RegDefs, SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) { SmallSet<unsigned, 32> &RegUses) {
if (candidate->isImplicitDef() || candidate->isKill()) if (candidate->isImplicitDef() || candidate->isKill())

6
lib/Target/Mips/MipsISelDAGToDAG.cpp
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@ -315,8 +315,10 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
DestReg = Mips::V1_64; DestReg = Mips::V1_64;
} }
SDNode *Rdhwr = CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), SDNode *Rdhwr =
Node->getValueType(0), CurDAG->getRegister(SrcReg, PtrVT)); CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
Node->getValueType(0),
CurDAG->getRegister(SrcReg, PtrVT));
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
SDValue(Rdhwr, 0)); SDValue(Rdhwr, 0));
SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);

92
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -297,8 +297,7 @@ static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
// create MipsMAdd(u) node // create MipsMAdd(u) node
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
SDValue MAdd = CurDAG->getNode(MultOpc, dl, SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
MVT::Glue,
MultNode->getOperand(0),// Factor 0 MultNode->getOperand(0),// Factor 0
MultNode->getOperand(1),// Factor 1 MultNode->getOperand(1),// Factor 1
ADDCNode->getOperand(1),// Lo0 ADDCNode->getOperand(1),// Lo0
@ -371,8 +370,7 @@ static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
// create MipsSub(u) node // create MipsSub(u) node
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
SDValue MSub = CurDAG->getNode(MultOpc, dl, SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
MVT::Glue,
MultNode->getOperand(0),// Factor 0 MultNode->getOperand(0),// Factor 0
MultNode->getOperand(1),// Factor 1 MultNode->getOperand(1),// Factor 1
SUBCNode->getOperand(0),// Lo0 SUBCNode->getOperand(0),// Lo0
@ -490,11 +488,10 @@ static bool InvertFPCondCode(Mips::CondCode CC) {
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
return false; return false;
if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
return true; "Illegal Condition Code");
assert(false && "Illegal Condition Code"); return true;
return false;
} }
// Creates and returns an FPCmp node from a setcc node. // Creates and returns an FPCmp node from a setcc node.
@ -584,8 +581,7 @@ static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
return SDValue(); return SDValue();
return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
ShiftRight.getOperand(0), ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
DAG.getConstant(Pos, MVT::i32),
DAG.getConstant(SMSize, MVT::i32)); DAG.getConstant(SMSize, MVT::i32));
} }
@ -638,11 +634,9 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
return SDValue(); return SDValue();
return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Shl.getOperand(0),
DAG.getConstant(SMPos0, MVT::i32), DAG.getConstant(SMPos0, MVT::i32),
DAG.getConstant(SMSize0, MVT::i32), DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
And0.getOperand(0));
} }
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
@ -713,10 +707,10 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
return Mips::BRANCH_T; return Mips::BRANCH_T;
if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
return Mips::BRANCH_F; "Invalid CondCode.");
return Mips::BRANCH_INVALID; return Mips::BRANCH_F;
} }
/* /*
@ -1049,8 +1043,7 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
// Transfer the remainder of BB and its successor edges to exitMBB. // Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB, exitMBB->splice(exitMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)), llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
BB->end());
exitMBB->transferSuccessorsAndUpdatePHIs(BB); exitMBB->transferSuccessorsAndUpdatePHIs(BB);
BB->addSuccessor(loopMBB); BB->addSuccessor(loopMBB);
@ -1082,7 +1075,6 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
// atomic.load.binop // atomic.load.binop
// loopMBB: // loopMBB:
// ll oldval,0(alignedaddr) // ll oldval,0(alignedaddr)
@ -1201,8 +1193,7 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
// Transfer the remainder of BB and its successor edges to exitMBB. // Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB, exitMBB->splice(exitMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)), llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
BB->end());
exitMBB->transferSuccessorsAndUpdatePHIs(BB); exitMBB->transferSuccessorsAndUpdatePHIs(BB);
// thisMBB: // thisMBB:
@ -1290,8 +1281,7 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
// Transfer the remainder of BB and its successor edges to exitMBB. // Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB, exitMBB->splice(exitMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)), llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
BB->end());
exitMBB->transferSuccessorsAndUpdatePHIs(BB); exitMBB->transferSuccessorsAndUpdatePHIs(BB);
BB->addSuccessor(loop1MBB); BB->addSuccessor(loop1MBB);
@ -1493,9 +1483,8 @@ SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
(HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GA); GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GA);
SDValue ResNode = DAG.getLoad(ValTy, dl, SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
DAG.getEntryNode(), GA, MachinePointerInfo(), MachinePointerInfo(), false, false, false, 0);
false, false, false, 0);
// On functions and global targets not internal linked only // On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work. // a load from got/GP is necessary for PIC to work.
if (!HasGotOfst) if (!HasGotOfst)
@ -1515,10 +1504,8 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
// %hi/%lo relocation // %hi/%lo relocation
SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
MipsII::MO_ABS_HI); SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
MipsII::MO_ABS_LO);
SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
@ -1530,8 +1517,7 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag); SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, BAGOTOffset); BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, BAGOTOffset);
SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag); SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
SDValue Load = DAG.getLoad(ValTy, dl, SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
DAG.getEntryNode(), BAGOTOffset,
MachinePointerInfo(), false, false, false, 0); MachinePointerInfo(), false, false, false, 0);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
@ -1672,9 +1658,9 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
N->getOffset(), GOTFlag); N->getOffset(), GOTFlag);
CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, CP); CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, CP);
SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
CP, MachinePointerInfo::getConstantPool(), MachinePointerInfo::getConstantPool(), false,
false, false, false, 0); false, false, 0);
SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
N->getOffset(), OFSTFlag); N->getOffset(), OFSTFlag);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
@ -1696,8 +1682,7 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
// memory location argument. // memory location argument.
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
MachinePointerInfo(SV), MachinePointerInfo(SV), false, false, 0);
false, false, 0);
} }
// Called if the size of integer registers is large enough to hold the whole // Called if the size of integer registers is large enough to hold the whole
@ -1750,15 +1735,15 @@ LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) {
return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
} }
SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) SDValue
const { MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
EVT Ty = Op.getValueType(); EVT Ty = Op.getValueType();
assert(Ty == MVT::f32 || Ty == MVT::f64); assert(Ty == MVT::f32 || Ty == MVT::f64);
if (Ty == MVT::f32 || HasMips64) if (Ty == MVT::f32 || HasMips64)
return LowerFCOPYSIGNLargeIntReg(Op, DAG); return LowerFCOPYSIGNLargeIntReg(Op, DAG);
else
return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle()); return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle());
} }
@ -1778,8 +1763,8 @@ LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
} }
// TODO: set SType according to the desired memory barrier behavior. // TODO: set SType according to the desired memory barrier behavior.
SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SDValue
SelectionDAG& DAG) const { MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
unsigned SType = 0; unsigned SType = 0;
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
@ -2007,9 +1992,8 @@ WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
DAG.getConstant(Offset, MVT::i32)); DAG.getConstant(Offset, MVT::i32));
SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
MachinePointerInfo(), MachinePointerInfo(), false, false, false,
false, false, false, std::min(ByValAlign, std::min(ByValAlign, (unsigned )4));
(unsigned )4));
MemOpChains.push_back(LoadVal.getValue(1)); MemOpChains.push_back(LoadVal.getValue(1));
unsigned DstReg = O32IntRegs[LocMemOffset / 4]; unsigned DstReg = O32IntRegs[LocMemOffset / 4];
RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
@ -2323,8 +2307,7 @@ MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
// emit ISD::STORE whichs stores the // emit ISD::STORE whichs stores the
// parameter value to a stack Location // parameter value to a stack Location
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo(), MachinePointerInfo(), false, false, 0));
false, false, 0));
} }
// Extend range of indices of frame objects for outgoing arguments that were // Extend range of indices of frame objects for outgoing arguments that were
@ -2376,8 +2359,8 @@ MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
OpFlag = MipsII::MO_NO_FLAG; OpFlag = MipsII::MO_NO_FLAG;
else // O32 & PIC else // O32 & PIC
OpFlag = MipsII::MO_GOT_CALL; OpFlag = MipsII::MO_GOT_CALL;
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
getPointerTy(), OpFlag); OpFlag);
GlobalOrExternal = true; GlobalOrExternal = true;
} }
@ -2552,8 +2535,7 @@ SDValue
MipsTargetLowering::LowerFormalArguments(SDValue Chain, MipsTargetLowering::LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, CallingConv::ID CallConv,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg> &Ins,
&Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) SmallVectorImpl<SDValue> &InVals)
const { const {
@ -2719,8 +2701,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true); LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
MachinePointerInfo(), MachinePointerInfo(), false, false, 0));
false, false, 0));
} }
} }
@ -2774,8 +2755,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
CCValAssign &VA = RVLocs[i]; CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!"); assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
OutVals[i], Flag);
// guarantee that all emitted copies are // guarantee that all emitted copies are
// stuck together, avoiding something bad // stuck together, avoiding something bad

14
lib/Target/Mips/MipsInstrInfo.td
View File

@ -229,24 +229,26 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pattern fragment for load/store // Pattern fragment for load/store
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{ class UnalignedLoad<PatFrag Node> :
PatFrag<(ops node:$ptr), (Node node:$ptr), [{
LoadSDNode *LD = cast<LoadSDNode>(N); LoadSDNode *LD = cast<LoadSDNode>(N);
return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment(); return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
}]>; }]>;
class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{ class AlignedLoad<PatFrag Node> :
PatFrag<(ops node:$ptr), (Node node:$ptr), [{
LoadSDNode *LD = cast<LoadSDNode>(N); LoadSDNode *LD = cast<LoadSDNode>(N);
return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment(); return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
}]>; }]>;
class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr), class UnalignedStore<PatFrag Node> :
(Node node:$val, node:$ptr), [{ PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
StoreSDNode *SD = cast<StoreSDNode>(N); StoreSDNode *SD = cast<StoreSDNode>(N);
return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment(); return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
}]>; }]>;
class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr), class AlignedStore<PatFrag Node> :
(Node node:$val, node:$ptr), [{ PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
StoreSDNode *SD = cast<StoreSDNode>(N); StoreSDNode *SD = cast<StoreSDNode>(N);
return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment(); return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
}]>; }]>;