From 82203218d1d801e5c0bdc33fe6afac2e91939a03 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 27 Oct 2010 18:17:12 +0000 Subject: [PATCH] Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117469 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/neon-mov-encoding.ll | 138 +++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/test/MC/ARM/neon-mov-encoding.ll b/test/MC/ARM/neon-mov-encoding.ll index 68edaed2ef9..2f8282b7c1f 100644 --- a/test/MC/ARM/neon-mov-encoding.ll +++ b/test/MC/ARM/neon-mov-encoding.ll @@ -167,3 +167,141 @@ define <2 x i32> @vmvn_2xi32f() nounwind { ; CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] ret <2 x i32> < i32 4292804608, i32 4292804608 > } + +define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A +; CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2] + %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A +; CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2] + %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A +; CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2] + %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> + ret <2 x i64> %tmp2 +} + +define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { + %tmp1 = load <8 x i8>* %A +; CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3] + %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { + %tmp1 = load <4 x i16>* %A +; CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3] + %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { + %tmp1 = load <2 x i32>* %A +; CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3] + %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> + ret <2 x i64> %tmp2 +} + +define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A +; CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3] + %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8> + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A +; CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3] + %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A +; CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3] + %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A +; CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3] + %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A +; CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3] + %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A +; CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3] + %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A +; CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3] + %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A +; CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3] + %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A +; CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3] + %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { + %tmp1 = load <8 x i16>* %A +; CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3] + %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { + %tmp1 = load <4 x i32>* %A +; CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] + %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind { + %tmp1 = load <2 x i64>* %A +; CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] + %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1) + ret <2 x i32> %tmp2 +} + +declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone + +declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone \ No newline at end of file