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lib/Target/SparcV9/RegAlloc/Notes.txt
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lib/Target/SparcV9/RegAlloc/Notes.txt
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===================
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Register Allocation
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===================
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1. Introduction
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===============
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Purpose: This file contains implementation information about register
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allocation.
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Author : Ruchira Sasanka
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Date : Dec 8, 2001
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2. Entry Point
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==============
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class PhyRegAlloc (PhyRegAlloc.h) is the main class for the register
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allocation. PhyRegAlloc::allocateRegisters() starts the register allocation
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and contains the major steps for register allocation.
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2. Usage
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========
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Register allocation must be done as:
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MethodLiveVarInfo LVI(*MethodI ); // compute LV info
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LVI.analyze();
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TargetMachine &target = .... // target description
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PhyRegAlloc PRA(*MethodI, target, &LVI); // allocate regs
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PRA.allocateRegisters();
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4. Input and Preconditions
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==========================
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Register allocation is done using machine instructions. The constructor
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to the class takes a pointer to a method, a target machine description and
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a live variable information for the method.
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The preconditions are:
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1. Instruction selection is complete (i.e., machine instructions are
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generated) for the method before the live variable analysis
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2. Phi elimination is complete.
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5. Assumptions
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==============
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All variables (llvm Values) are defined before they are used. However, a
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constant may not be defined in the machine instruction stream if it can be
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used as an immediate value within a machine instruction. However, register
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allocation does not have to worry about immediate constants since they
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do not require registers.
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Since an llvm Value has a list of uses associated, it is sufficient to
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record only the defs in a Live Range.
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6. Overall Design
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=================
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There are sperate reigster classes - e.g., Int, Float,
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IntConditionCode, FloatConditionCode register classes for Sparc.
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Registerallocation consists of the following main steps:
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1. Construct Live-ranges & Suggest colors (machine specific) if required
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2. Create Interference graphs
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3. Coalescing live ranges
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4. Color all live ranges in each RegClass using graph coloring algo
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5. Insert additional (machine specific) code for calls/returns/incoming args
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6. Update instruction stream and insert spill code
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All the above methods are called from PhyRegAlloc::allocateRegisters().
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All steps above except step 5 and suggesting colors in step 1 are indepenedent
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of a particular target architecture. Targer independent code is availble in
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../lib/CodeGen/RegAlloc. Target specific code for Sparc is available in
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../lib/Target/Sparc.
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6.1. Construct Live-ranges & Suggest colors (machine specific) if required
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--------------------------------------------------------------------------
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Live range construction is done using machine instructions. Since there must
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be at least one definition for each variable in the machine instruction, we
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consider only definitions in creating live ranges. After live range
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construction is complete, there is a live range for all variables defined in
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the instruction stream. Note however that, live ranges are not constructed for
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constants which are not defined in the instruction stream.
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A LiveRange is a set of Values (only defs) in that live range. Live range
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construction is done in combination for all register classes. All the live
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ranges for a method are entered to a LiveRangeMap which can be accessed using
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any Value in the LiveRange.
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After live ranges have been constructed, we call machine specific code to
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suggest colors for speical live ranges. For instance, incoming args, call args,
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return values must be placed in special registers for most architectures. By
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suggesting colors for such special live ranges before we do the actual register
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allocation using graph coloring, the graph coloring can try its best to assign
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the required color for such special live ranges. This will reduce unnecessary
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copy instructions needed to move values to special registers. However, there
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is no guarantee that a live range will receive its suggested color. If the
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live range does not receive the suggested color, we have to insert explicit
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copy instructions to move the value into requred registers and its done in
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step 5 above.
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See LiveRange.h, LiveRangeInfo.h (and LiveRange.cpp, LiveRangeInfo.cpp) for
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algorithms and details. See SparcRegInfo.cpp for suggesting colors for
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incoming/call arguments and return values.
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6.2. Create Interference graphs
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-------------------------------
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Once live ranges are constructed, we can build interference graphs for each
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register class. Though each register class must have a separate interference
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graph, building all interference graphs is performed in one pass. Also, the
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adjacency list for each live range is built in this phase. Consequently, each
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register class has an interference graph (which is a bit matrix) and each
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LiveRange has an adjacency list to record its neighbors. Live variable info
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is used for finding the interferences.
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See IGNode.h, InterferenceGraph.h (and IGNode.h, InterferenceGraph.h) for
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data structures and PhyRegAlloc::createIGNodeListsAndIGs() for the starting
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point for interference graph construction.
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6.3. Coalescing live ranges
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---------------------------
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We coalesce live ranges to reduce the number of live ranges.
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See LiveRangeInfo.h (and LiveRangeInfo.cpp). The entire algorithm for
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coalesing is given in LiveRangeInfo::coalesceLRs().
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6.4. Color all live ranges in each RegClass using graph coloring algo
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---------------------------------------------------------------------
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Each register class is colored separately using the graph coloring algo. When
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assigning colors, preference is given to live ranges with suggested colors
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so that if such a live range receives a color (i.e., not spilled), then
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we try to assign the color suggested for that live range. When this phase
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is complete it is possible that some live ranges do not have colors (i.e.,
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those that must be spilled).
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6.5. Insert additional (machine specific) code for calls/returns/incoming args
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------------------------------------------------------------------------------
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This code is machine specific. Currently, the code for Sparc is implemented
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in SparcRegInfo.cpp. This code is more complex because of the complex
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requirements of assigning some values to special registers. When a special
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value as an incoming argument receives a color through the graph coloring
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alogorithm, we have to make sure that it received the correct color (for
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instance the first incoming int argument must be colored to %i0 on Sparc). If
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it didn't receive the correct color, we have to insert instruction to to move
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the value to the required register. Also, this phase produces the caller
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saving code. All adition code produced is kept separately until the last
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phase (see 6.6)
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6.6. Update instruction stream and insert spill code
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-----------------------------------------------------
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After we have assigned registers for all values and after we have produced
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additional code to be inserted before some instructions, we update the
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machine instruction stream. While we are updating the machine instruction
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stream, if an instruction referes to a spilled value, we insert spill
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instructions before/after that instruction. Also, we prepend/append additonal
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instructions that have been produced for that instruction by the register
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allocation (e.g., caller saving code)
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7. Furture work
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===============
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If it is necessary to port the register allocator to another architecture
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than Sparc, only the target specific code in ../lib/Target/Sparc needs to
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be rewritten. Methods defined in class MachineRegInfo must be provided for
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the new architecure.
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7.1 Using ReservedColorList in RegClass
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----------------------------------------
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The register allocator allows reserving a set of registers - i.e. the reserved
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registers are not used by the register allocator. Currently, there are no
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reserved registers. It it is necessary to make some registers unavailable to
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a particular method, this feature will become handy. To do that, the reserved
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register list must be passed to the register allocator. See PhyRegAlloc.cpp
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7.2 %g registers on Sparc
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-------------------------
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Currently, %g registers are not allocated on Sparc. If it is necessary to
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allocate these %g registers, the enumeration of registers in SparcIntRegClass
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in SparcRegClassInfo.h must be changed. %g registers can be easily added as
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volatile registers just by moving them above in the eneumeration - see
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SparcRegClassInfo.h
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