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Emit stores correctly; don't fail an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14209 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -479,7 +479,7 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
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// Printing memory instructions is a special case.
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// for loads: %dest = op %base, offset --> op [%base + offset], %dest
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// for stores: op %src, %base, offset --> op %src, [%base + offset]
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// for stores: op %base, offset, %src --> op %src, [%base + offset]
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if (isLoadInstruction (MI)) {
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printBaseOffsetPair (MI, 1);
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O << ", ";
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@ -487,9 +487,9 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
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O << "\n";
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return;
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} else if (isStoreInstruction (MI)) {
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printOperand (MI, 0);
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printOperand (MI, 2);
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O << ", ";
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printBaseOffsetPair (MI, 1);
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printBaseOffsetPair (MI, 0);
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O << "\n";
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return;
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}
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@ -479,7 +479,7 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
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// Printing memory instructions is a special case.
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// for loads: %dest = op %base, offset --> op [%base + offset], %dest
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// for stores: op %src, %base, offset --> op %src, [%base + offset]
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// for stores: op %base, offset, %src --> op %src, [%base + offset]
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if (isLoadInstruction (MI)) {
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printBaseOffsetPair (MI, 1);
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O << ", ";
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@ -487,9 +487,9 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
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O << "\n";
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return;
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} else if (isStoreInstruction (MI)) {
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printOperand (MI, 0);
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printOperand (MI, 2);
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O << ", ";
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printBaseOffsetPair (MI, 1);
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printBaseOffsetPair (MI, 0);
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O << "\n";
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return;
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}
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