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switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This

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speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-02-04 08:47:20 +00:00
parent 3f97eb449b
commit 831e0374a7
3 changed files with 8 additions and 8 deletions
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4
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -240,7 +240,7 @@ namespace llvm {
/// VRBaseMap contains, for each already emitted node, the first virtual
/// register number for the results of the node.
///
void EmitNode(SDNode *Node, std::map<SDNode*, unsigned> &VRBaseMap);
void EmitNode(SDNode *Node, DenseMap<SDNode*, unsigned> &VRBaseMap);
/// EmitNoop - Emit a noop instruction.
///
@ -257,7 +257,7 @@ namespace llvm {
private:
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
const TargetInstrDescriptor *II,
std::map<SDNode*, unsigned> &VRBaseMap);
DenseMap<SDNode*, unsigned> &VRBaseMap);
};
/// createBFS_DAGScheduler - This creates a simple breadth first instruction

10
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -269,8 +269,8 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) {
DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second + Op.ResNo;
}
@ -283,7 +283,7 @@ static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
const TargetInstrDescriptor *II,
std::map<SDNode*, unsigned> &VRBaseMap) {
DenseMap<SDNode*, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@ -371,7 +371,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node,
std::map<SDNode*, unsigned> &VRBaseMap) {
DenseMap<SDNode*, unsigned> &VRBaseMap) {
unsigned VRBase = 0; // First virtual register for node
// If machine instruction
@ -595,7 +595,7 @@ void ScheduleDAG::EmitSchedule() {
// Finally, emit the code for all of the scheduled instructions.
std::map<SDNode*, unsigned> VRBaseMap;
DenseMap<SDNode*, unsigned> VRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) {
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)

2
lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
View File

@ -682,7 +682,7 @@ void ScheduleDAGSimple::EmitAll() {
LI->first, RegMap->getRegClass(LI->second));
}
std::map<SDNode*, unsigned> VRBaseMap;
DenseMap<SDNode*, unsigned> VRBaseMap;
// For each node in the ordering
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {