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Don't handle -arm-long-calls in fast isel for now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-12-15 23:47:29 +00:00
parent d0bb5e2ca0
commit 836c6245ad
3 changed files with 39 additions and 1 deletions
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8
lib/Target/ARM/ARMFastISel.cpp
View File

@ -52,6 +52,8 @@ DisableARMFastISel("disable-arm-fast-isel",
cl::desc("Turn off experimental ARM fast-isel support"),
cl::init(false), cl::Hidden);
extern cl::opt<bool> EnableARMLongCalls;
namespace {
// All possible address modes, plus some.
@ -1656,6 +1658,9 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
// For now we're using BLX etc on the assumption that we have v5t ops.
if (!Subtarget->hasV5TOps()) return false;
// TODO: For now if we have long calls specified we don't handle the call.
if (EnableARMLongCalls) return false;
// Set up the argument vectors.
SmallVector<Value*, 8> Args;
SmallVector<unsigned, 8> ArgRegs;
@ -1753,6 +1758,9 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
// TODO: Maybe?
if (!Subtarget->hasV5TOps()) return false;
// TODO: For now if we have long calls specified we don't handle the call.
if (EnableARMLongCalls) return false;
// Set up the argument vectors.
SmallVector<Value*, 8> Args;
SmallVector<unsigned, 8> ArgRegs;

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -59,7 +59,7 @@ EnableARMTailCalls("arm-tail-calls", cl::Hidden,
cl::desc("Generate tail calls (TEMPORARY OPTION)."),
cl::init(false));
static cl::opt<bool>
cl::opt<bool>
EnableARMLongCalls("arm-long-calls", cl::Hidden,
cl::desc("Generate calls via indirect call instructions"),
cl::init(false));

30
test/CodeGen/ARM/fast-isel-static.ll Normal file
View File

@ -0,0 +1,30 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -relocation-model=static | FileCheck -check-prefix=NORM %s
define void @myadd(float* %sum, float* %addend) nounwind {
entry:
%sum.addr = alloca float*, align 4
%addend.addr = alloca float*, align 4
store float* %sum, float** %sum.addr, align 4
store float* %addend, float** %addend.addr, align 4
%tmp = load float** %sum.addr, align 4
%tmp1 = load float* %tmp
%tmp2 = load float** %addend.addr, align 4
%tmp3 = load float* %tmp2
%add = fadd float %tmp1, %tmp3
%tmp4 = load float** %sum.addr, align 4
store float %add, float* %tmp4
ret void
}
define i32 @main(i32 %argc, i8** %argv) nounwind {
entry:
%ztot = alloca float, align 4
%z = alloca float, align 4
store float 0.000000e+00, float* %ztot, align 4
store float 1.000000e+00, float* %z, align 4
; CHECK-LONG: blx r2
; CHECK-NORM: blx _myadd
call void @myadd(float* %ztot, float* %z)
ret i32 0
}