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[mips] Fix FP branch instructions to have explicit FP condition code register
operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
ce0a12399c
commit
83d8ef133b
@ -123,6 +123,11 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -158,12 +163,6 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBC1(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -407,6 +406,17 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 7)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -529,16 +539,6 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBC1(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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unsigned BranchOffset = Insn & 0xffff;
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BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -245,6 +245,14 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
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if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
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return true;
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break;
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case Mips::BC1T:
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if (isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS))
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return true;
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break;
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case Mips::BC1F:
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if (isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS))
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return true;
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break;
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case Mips::OR:
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if (isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS))
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return true;
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@ -1438,8 +1438,9 @@ lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
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(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
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unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
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SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
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SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
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return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
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Dest, CondRes);
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FCC0, Dest, CondRes);
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}
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SDValue MipsTargetLowering::
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@ -24,8 +24,9 @@
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//===----------------------------------------------------------------------===//
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// Floating Point Compare and Branch
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def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
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SDTCisVT<1, OtherVT>]>;
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def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
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SDTCisVT<1, i32>,
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SDTCisVT<2, OtherVT>]>;
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def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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SDTCisVT<2, i32>]>;
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def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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@ -188,13 +189,13 @@ class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
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class BC1F_FT<string opstr, InstrItinClass Itin,
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SDPatternOperator Op = null_frag> :
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InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
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[(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
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InstSE<(outs), (ins FCC:$fcc, brtarget:$offset),
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!strconcat(opstr, "\t$fcc, $offset"),
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[(MipsFPBrcond Op, FCC:$fcc, bb:$offset)], Itin, FrmFI> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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let Uses = [FCC0];
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}
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class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
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@ -502,10 +503,9 @@ let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
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def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
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def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
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let DecoderMethod = "DecodeBC1" in {
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def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
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def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Flag Conditions
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//===----------------------------------------------------------------------===//
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@ -557,6 +557,12 @@ def ExtractElementF64 :
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[(set CPURegsOpnd:$dst,
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(MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>;
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//===----------------------------------------------------------------------===//
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// InstAliases.
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//===----------------------------------------------------------------------===//
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def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>;
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def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>;
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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//===----------------------------------------------------------------------===//
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@ -665,13 +665,14 @@ class SWXC1_FM<bits<6> funct> {
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}
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class BC1F_FM<bit nd, bit tf> {
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bits<3> fcc;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = 0x8;
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let Inst{20-18} = 0; // cc
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let Inst{20-18} = fcc;
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let Inst{17} = nd;
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let Inst{16} = tf;
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let Inst{15-0} = offset;
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@ -35,9 +35,15 @@
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# CHECK: bc1f 1332
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0x45 0x00 0x01 0x4c
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# CHECK: bc1f $fcc7, 1332
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0x45 0x1c 0x01 0x4c
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# CHECK: bc1t 1332
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0x45 0x01 0x01 0x4c
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# CHECK: bc1t $fcc7, 1332
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0x45 0x1d 0x01 0x4c
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# CHECK: beq $9, $6, 1332
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0x11 0x26 0x01 0x4c
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@ -35,9 +35,15 @@
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# CHECK: bc1f 1332
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0x4c 0x01 0x00 0x45
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# CHECK: bc1f $fcc7, 1332
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0x4c 0x01 0x1c 0x45
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# CHECK: bc1t 1332
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0x4c 0x01 0x01 0x45
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# CHECK: bc1t $fcc7, 1332
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0x4c 0x01 0x1d 0x45
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# CHECK: beq $9, $6, 1332
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0x4c 0x01 0x26 0x11
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@ -35,9 +35,15 @@
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# CHECK: bc1f 1332
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0x45 0x00 0x01 0x4c
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# CHECK: bc1f $fcc7, 1332
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0x45 0x1c 0x01 0x4c
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# CHECK: bc1t 1332
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0x45 0x01 0x01 0x4c
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# CHECK: bc1t $fcc7, 1332
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0x45 0x1d 0x01 0x4c
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# CHECK: beq $9, $6, 1332
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0x11 0x26 0x01 0x4c
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@ -35,9 +35,15 @@
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# CHECK: bc1f 1332
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0x4c 0x01 0x00 0x45
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# CHECK: bc1f $fcc7, 1332
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0x4c 0x01 0x1c 0x45
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# CHECK: bc1t 1332
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0x4c 0x01 0x01 0x45
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# CHECK: bc1t $fcc7, 1332
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0x4c 0x01 0x1d 0x45
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# CHECK: beq $9, $6, 1332
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0x4c 0x01 0x26 0x11
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