mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-18 07:52:35 +00:00
ARM64: nick some AArch64 patterns for extract/insert -> INS.
Tests will be committed shortly when all optimisations needed to support AArch64's neon-copy.ll file are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
66643da8fc
commit
8405c940d3
@ -3137,6 +3137,43 @@ def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
|
||||
V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
|
||||
)>;
|
||||
|
||||
multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
|
||||
ValueType VTScal, Instruction INS> {
|
||||
def : Pat<(VT128 (vector_insert V128:$src,
|
||||
(VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
|
||||
imm:$Immd)),
|
||||
(INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
|
||||
|
||||
def : Pat<(VT128 (vector_insert V128:$src,
|
||||
(VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
|
||||
imm:$Immd)),
|
||||
(INS V128:$src, imm:$Immd,
|
||||
(SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
|
||||
|
||||
def : Pat<(VT64 (vector_insert V64:$src,
|
||||
(VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
|
||||
imm:$Immd)),
|
||||
(EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
|
||||
imm:$Immd, V128:$Rn, imm:$Immn),
|
||||
dsub)>;
|
||||
|
||||
def : Pat<(VT64 (vector_insert V64:$src,
|
||||
(VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
|
||||
imm:$Immd)),
|
||||
(EXTRACT_SUBREG
|
||||
(INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
|
||||
(SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
|
||||
dsub)>;
|
||||
}
|
||||
|
||||
defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
|
||||
defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
|
||||
defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
|
||||
defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
|
||||
defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
|
||||
defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
|
||||
|
||||
|
||||
// Floating point vector extractions are codegen'd as either a sequence of
|
||||
// subregister extractions, possibly fed by an INS if the lane number is
|
||||
// anything other than zero.
|
||||
|
Loading…
x
Reference in New Issue
Block a user