mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-16 16:37:42 +00:00
Reverting 178851 as it broke buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178883 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin
parent
e112453fc3
commit
84581daf20
@ -87,53 +87,6 @@ namespace {
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MachineBasicBlock::iterator i)
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: Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
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};
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class UnitRegsMap {
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public:
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UnitRegsMap(const TargetRegisterInfo* _TRI) : TRI(_TRI) {}
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const SmallVector<unsigned, 4>& operator[](unsigned Reg) {
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DenseMap<unsigned, SmallVector<unsigned, 4> >::iterator found =
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Cache.find(Reg);
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if (found != Cache.end())
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return found->second;
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else
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return Cache.insert(std::make_pair(Reg, this->getUnitRegs(Reg)))
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.first->second;
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}
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private:
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SmallVector<unsigned, 4> getUnitRegs(unsigned Reg) {
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SmallVector<unsigned, 4> Res;
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const TargetRegisterClass* TRC = TRI->getMinimalPhysRegClass(Reg);
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if (TRC == &ARM::QPRRegClass) {
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if (Reg > ARM::Q7) {
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Res.push_back(TRI->getSubReg(Reg, ARM::dsub_0));
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Res.push_back(TRI->getSubReg(Reg, ARM::dsub_1));
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return Res;
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}
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Res.push_back(TRI->getSubReg(Reg, ARM::ssub_0));
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Res.push_back(TRI->getSubReg(Reg, ARM::ssub_1));
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Res.push_back(TRI->getSubReg(Reg, ARM::ssub_2));
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Res.push_back(TRI->getSubReg(Reg, ARM::ssub_3));
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return Res;
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}
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if (TRC == &ARM::DPRRegClass && Reg < ARM::D15) {
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Res.push_back(TRI->getSubReg(Reg, ARM::ssub_0));
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Res.push_back(TRI->getSubReg(Reg, ARM::ssub_1));
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return Res;
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}
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Res.push_back(Reg);
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return Res;
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}
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const TargetRegisterInfo* TRI;
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DenseMap<unsigned, SmallVector<unsigned, 4> > Cache;
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};
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typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
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typedef MemOpQueue::iterator MemOpQueueIter;
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@ -175,11 +128,6 @@ namespace {
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MachineBasicBlock::iterator MBBI,
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bool &Advance,
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MachineBasicBlock::iterator &I);
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unsigned AddMemOp(MemOpQueue& MemOps,
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const MemOpQueueEntry newEntry,
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UnitRegsMap& UnitRegsInfo,
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SmallSet<unsigned, 4>& UsedUnitRegs,
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unsigned At = -1U);
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bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
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bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
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};
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@ -1265,103 +1213,12 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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return false;
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}
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/// AddMemOp - helper for ARMLoadStoreOpt::LoadStoreMultipleOpti.
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/// It adds store mem ops with simple push_back/insert method,
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/// without any additional logic.
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/// For load operation it does the next:
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/// 1. Adds new load operation into MemOp collection at "At" position.
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/// 2. Removes any "load" operations from MemOps, that changes "Reg" register
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/// contents, prior to "At".
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/// UnitRegsInfo - Map of type Map< Register, UnitRegisters-vector >
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/// UsedUnitRegs - set of unit-registers currently in use.
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/// At - position at which it would added, and prior which the clean-up
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/// should be made (for load operation).
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/// FIXME: The clean-up also should be made for store operations,
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/// but the memory address should be analyzed instead of unit registers.
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unsigned ARMLoadStoreOpt::AddMemOp(MemOpQueue& MemOps,
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const MemOpQueueEntry NewEntry,
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UnitRegsMap& UnitRegsInfo,
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SmallSet<unsigned, 4>& UsedUnitRegs,
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unsigned At) {
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unsigned Cleaned = 0;
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if (At == -1U) {
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At = MemOps.size();
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MemOps.push_back(NewEntry);
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} else
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MemOps.insert(&MemOps[At], NewEntry);
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// FIXME:
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// If operation is not load, leave it as is by now,
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// So 0 overridden ops would cleaned in this case.
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if (!NewEntry.MBBI->mayLoad())
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return 0;
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const SmallVector<unsigned, 4>& NewEntryUnitRegs = UnitRegsInfo[NewEntry.Reg];
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bool FoundOverriddenLoads = false;
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for (unsigned i = 0, e = NewEntryUnitRegs.size(); i != e; ++i)
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if (UsedUnitRegs.count(NewEntryUnitRegs[i])) {
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FoundOverriddenLoads = true;
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break;
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}
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// If we detect that this register is used by load operations that are
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// predecessors for the new one, remove them from MemOps then.
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if (FoundOverriddenLoads) {
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MemOpQueue UpdatedMemOps;
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// Scan through MemOps entries.
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for (unsigned i = 0; i != At; ++i) {
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MemOpQueueEntry& MemOpEntry = MemOps[i];
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// FIXME: Skip non-load operations by now.
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if (!MemOpEntry.MBBI->mayLoad())
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continue;
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const SmallVector<unsigned, 4>& MemOpUnitRegs =
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UnitRegsInfo[MemOpEntry.Reg];
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// Lookup entry that loads contents into register used by new entry.
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bool ReleaseThisEntry = false;
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for (unsigned m = 0, em = MemOpUnitRegs.size(); m != em; ++m) {
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if (std::find(NewEntryUnitRegs.begin(), NewEntryUnitRegs.end(),
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MemOpUnitRegs[m]) != NewEntryUnitRegs.end()) {
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ReleaseThisEntry = true;
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++Cleaned;
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break;
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}
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}
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if (ReleaseThisEntry) {
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const SmallVector<unsigned, 4>& RelesedRegs = UnitRegsInfo[MemOpEntry.Reg];
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for (unsigned r = 0, er = RelesedRegs.size(); r != er; ++r)
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UsedUnitRegs.erase(RelesedRegs[r]);
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} else
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UpdatedMemOps.push_back(MemOpEntry);
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}
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// Keep anything without changes after At position.
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for (unsigned i = At, e = MemOps.size(); i != e; ++i)
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UpdatedMemOps.push_back(MemOps[i]);
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MemOps.swap(UpdatedMemOps);
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}
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UsedUnitRegs.insert(NewEntryUnitRegs.begin(), NewEntryUnitRegs.end());
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return Cleaned;
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}
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/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
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/// ops of the same base and incrementing offset into LDM / STM ops.
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bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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unsigned NumMerges = 0;
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unsigned NumMemOps = 0;
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MemOpQueue MemOps;
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UnitRegsMap UnitRegsInfo(TRI);
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SmallSet<unsigned, 4> UsedRegUnits;
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unsigned CurrBase = 0;
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int CurrOpc = -1;
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unsigned CurrSize = 0;
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@ -1408,11 +1265,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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CurrSize = Size;
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CurrPred = Pred;
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CurrPredReg = PredReg;
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MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
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++NumMemOps;
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const SmallVector<unsigned, 4>& EntryUnitRegs = UnitRegsInfo[Reg];
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UsedRegUnits.insert(EntryUnitRegs.begin(), EntryUnitRegs.end());
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Advance = true;
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} else {
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if (Clobber) {
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@ -1424,24 +1278,20 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// No need to match PredReg.
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// Continue adding to the queue.
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if (Offset > MemOps.back().Offset) {
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unsigned OverridesCleaned =
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AddMemOp(MemOps,
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MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI),
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UnitRegsInfo, UsedRegUnits) != 0;
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NumMemOps += 1 - OverridesCleaned;
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MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill,
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Position, MBBI));
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++NumMemOps;
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Advance = true;
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} else {
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for (unsigned I = 0; I != NumMemOps; ++I) {
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if (Offset < MemOps[I].Offset) {
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MemOpQueueEntry entry(Offset, Reg, isKill, Position, MBBI);
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unsigned OverridesCleaned =
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AddMemOp(MemOps, entry, UnitRegsInfo,
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UsedRegUnits, I) != 0;
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NumMemOps += 1 - OverridesCleaned;
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for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
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I != E; ++I) {
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if (Offset < I->Offset) {
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MemOps.insert(I, MemOpQueueEntry(Offset, Reg, isKill,
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Position, MBBI));
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++NumMemOps;
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Advance = true;
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break;
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} else if (Offset == MemOps[I].Offset) {
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} else if (Offset == I->Offset) {
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// Collision! This can't be merged!
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break;
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}
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@ -1512,7 +1362,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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CurrPredReg = 0;
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if (NumMemOps) {
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MemOps.clear();
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UsedRegUnits.clear();
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NumMemOps = 0;
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}
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@ -1,110 +0,0 @@
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; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp | FileCheck %s
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; The test is presented by Jiangning Liu.
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;CHECK-NOT: vldmia
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define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i64> * %dest) nounwind {
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entry:
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%s0 = load <8 x i64> * %source, align 64
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%s1 = load <8 x i64> * %secondSource, align 64
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%s2 = bitcast <8 x i64> %s0 to i512
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%data.i.i.48.extract.shift = lshr i512 %s2, 384
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%data.i.i.48.extract.trunc = trunc i512 %data.i.i.48.extract.shift to i64
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%arrayidx64 = getelementptr inbounds <8 x i64> * %source, i32 6
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%s120 = load <8 x i64> * %arrayidx64, align 64
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%arrayidx67 = getelementptr inbounds <8 x i64> * %secondSource, i32 6
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%s121 = load <8 x i64> * %arrayidx67, align 64
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%s122 = bitcast <8 x i64> %s120 to i512
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%data.i.i677.48.extract.shift = lshr i512 %s122, 384
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%data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64
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%s123 = insertelement <8 x i64> undef, i64 %data.i.i677.48.extract.trunc, i32 0
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%data.i.i677.32.extract.shift = lshr i512 %s122, 256
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%data.i.i677.32.extract.trunc = trunc i512 %data.i.i677.32.extract.shift to i64
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%s124 = insertelement <8 x i64> %s123, i64 %data.i.i677.32.extract.trunc, i32 1
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%data.i.i677.16.extract.shift = lshr i512 %s122, 128
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%data.i.i677.16.extract.trunc = trunc i512 %data.i.i677.16.extract.shift to i64
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%s125 = insertelement <8 x i64> %s124, i64 %data.i.i677.16.extract.trunc, i32 2
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%data.i.i677.56.extract.shift = lshr i512 %s122, 448
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%data.i.i677.56.extract.trunc = trunc i512 %data.i.i677.56.extract.shift to i64
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%s126 = insertelement <8 x i64> %s125, i64 %data.i.i677.56.extract.trunc, i32 3
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%data.i.i677.24.extract.shift = lshr i512 %s122, 192
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%data.i.i677.24.extract.trunc = trunc i512 %data.i.i677.24.extract.shift to i64
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%s127 = insertelement <8 x i64> %s126, i64 %data.i.i677.24.extract.trunc, i32 4
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%s128 = insertelement <8 x i64> %s127, i64 %data.i.i677.32.extract.trunc, i32 5
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%s129 = insertelement <8 x i64> %s128, i64 %data.i.i677.16.extract.trunc, i32 6
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%s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7
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%s131 = bitcast <8 x i64> %s121 to i512
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%data.i1.i676.48.extract.shift = lshr i512 %s131, 384
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%data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64
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%s132 = insertelement <8 x i64> undef, i64 %data.i1.i676.48.extract.trunc, i32 0
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%data.i1.i676.32.extract.shift = lshr i512 %s131, 256
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%data.i1.i676.32.extract.trunc = trunc i512 %data.i1.i676.32.extract.shift to i64
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%s133 = insertelement <8 x i64> %s132, i64 %data.i1.i676.32.extract.trunc, i32 1
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%data.i1.i676.16.extract.shift = lshr i512 %s131, 128
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%data.i1.i676.16.extract.trunc = trunc i512 %data.i1.i676.16.extract.shift to i64
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%s134 = insertelement <8 x i64> %s133, i64 %data.i1.i676.16.extract.trunc, i32 2
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%data.i1.i676.56.extract.shift = lshr i512 %s131, 448
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%data.i1.i676.56.extract.trunc = trunc i512 %data.i1.i676.56.extract.shift to i64
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%s135 = insertelement <8 x i64> %s134, i64 %data.i1.i676.56.extract.trunc, i32 3
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%data.i1.i676.24.extract.shift = lshr i512 %s131, 192
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%data.i1.i676.24.extract.trunc = trunc i512 %data.i1.i676.24.extract.shift to i64
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%s136 = insertelement <8 x i64> %s135, i64 %data.i1.i676.24.extract.trunc, i32 4
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%s137 = insertelement <8 x i64> %s136, i64 %data.i1.i676.32.extract.trunc, i32 5
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%s138 = insertelement <8 x i64> %s137, i64 %data.i1.i676.16.extract.trunc, i32 6
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%s139 = insertelement <8 x i64> %s138, i64 %data.i1.i676.56.extract.trunc, i32 7
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%vecinit28.i.i699 = shufflevector <8 x i64> %s139, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 undef, i32 undef, i32 undef>
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%vecinit35.i.i700 = shufflevector <8 x i64> %vecinit28.i.i699, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef>
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%vecinit42.i.i701 = shufflevector <8 x i64> %vecinit35.i.i700, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef>
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%vecinit49.i.i702 = shufflevector <8 x i64> %vecinit42.i.i701, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
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%arrayidx72 = getelementptr inbounds <8 x i64> * %dest, i32 6
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store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64
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%arrayidx75 = getelementptr inbounds <8 x i64> * %source, i32 7
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%s140 = load <8 x i64> * %arrayidx75, align 64
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%arrayidx78 = getelementptr inbounds <8 x i64> * %secondSource, i32 7
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%s141 = load <8 x i64> * %arrayidx78, align 64
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%s142 = bitcast <8 x i64> %s140 to i512
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%data.i.i650.32.extract.shift = lshr i512 %s142, 256
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%data.i.i650.32.extract.trunc = trunc i512 %data.i.i650.32.extract.shift to i64
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%s143 = insertelement <8 x i64> undef, i64 %data.i.i650.32.extract.trunc, i32 0
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%s144 = insertelement <8 x i64> %s143, i64 %data.i.i650.32.extract.trunc, i32 1
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%data.i.i650.16.extract.shift = lshr i512 %s142, 128
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%data.i.i650.16.extract.trunc = trunc i512 %data.i.i650.16.extract.shift to i64
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%s145 = insertelement <8 x i64> %s144, i64 %data.i.i650.16.extract.trunc, i32 2
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%data.i.i650.8.extract.shift = lshr i512 %s142, 64
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%data.i.i650.8.extract.trunc = trunc i512 %data.i.i650.8.extract.shift to i64
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%s146 = insertelement <8 x i64> %s145, i64 %data.i.i650.8.extract.trunc, i32 3
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%s147 = insertelement <8 x i64> %s146, i64 %data.i.i650.8.extract.trunc, i32 4
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%data.i.i650.48.extract.shift = lshr i512 %s142, 384
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%data.i.i650.48.extract.trunc = trunc i512 %data.i.i650.48.extract.shift to i64
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%s148 = insertelement <8 x i64> %s147, i64 %data.i.i650.48.extract.trunc, i32 5
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%s149 = insertelement <8 x i64> %s148, i64 %data.i.i650.16.extract.trunc, i32 6
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%data.i.i650.0.extract.trunc = trunc i512 %s142 to i64
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%s150 = insertelement <8 x i64> %s149, i64 %data.i.i650.0.extract.trunc, i32 7
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%s151 = bitcast <8 x i64> %s141 to i512
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%data.i1.i649.32.extract.shift = lshr i512 %s151, 256
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%data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64
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%s152 = insertelement <8 x i64> undef, i64 %data.i1.i649.32.extract.trunc, i32 0
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%s153 = insertelement <8 x i64> %s152, i64 %data.i1.i649.32.extract.trunc, i32 1
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%data.i1.i649.16.extract.shift = lshr i512 %s151, 128
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%data.i1.i649.16.extract.trunc = trunc i512 %data.i1.i649.16.extract.shift to i64
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%s154 = insertelement <8 x i64> %s153, i64 %data.i1.i649.16.extract.trunc, i32 2
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%data.i1.i649.8.extract.shift = lshr i512 %s151, 64
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%data.i1.i649.8.extract.trunc = trunc i512 %data.i1.i649.8.extract.shift to i64
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%s155 = insertelement <8 x i64> %s154, i64 %data.i1.i649.8.extract.trunc, i32 3
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%s156 = insertelement <8 x i64> %s155, i64 %data.i1.i649.8.extract.trunc, i32 4
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%data.i1.i649.48.extract.shift = lshr i512 %s151, 384
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%data.i1.i649.48.extract.trunc = trunc i512 %data.i1.i649.48.extract.shift to i64
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%s157 = insertelement <8 x i64> %s156, i64 %data.i1.i649.48.extract.trunc, i32 5
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%s158 = insertelement <8 x i64> %s157, i64 %data.i1.i649.16.extract.trunc, i32 6
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%data.i1.i649.0.extract.trunc = trunc i512 %s151 to i64
|
||||
%s159 = insertelement <8 x i64> %s158, i64 %data.i1.i649.0.extract.trunc, i32 7
|
||||
%vecinit7.i.i669 = shufflevector <8 x i64> %s159, <8 x i64> %s150, <8 x i32> <i32 0, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%vecinit14.i.i670 = shufflevector <8 x i64> %vecinit7.i.i669, <8 x i64> %s150, <8 x i32> <i32 0, i32 1, i32 10, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%vecinit21.i.i671 = shufflevector <8 x i64> %vecinit14.i.i670, <8 x i64> %s150, <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
%vecinit28.i.i672 = shufflevector <8 x i64> %vecinit21.i.i671, <8 x i64> %s150, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 undef, i32 undef, i32 undef>
|
||||
%vecinit35.i.i673 = shufflevector <8 x i64> %vecinit28.i.i672, <8 x i64> %s159, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef>
|
||||
%vecinit42.i.i674 = shufflevector <8 x i64> %vecinit35.i.i673, <8 x i64> %s159, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef>
|
||||
%vecinit49.i.i675 = shufflevector <8 x i64> %vecinit42.i.i674, <8 x i64> %s159, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
|
||||
%arrayidx83 = getelementptr inbounds <8 x i64> * %dest, i32 7
|
||||
store <8 x i64> %vecinit49.i.i675, <8 x i64> * %arrayidx83, align 64
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user