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[AVX512] Suppress duplicate register only FMA patterns.
Previously we generated a register only pattern for each of the 3 instruction forms, but they are all identical as far as isel is concerned. So drop the others and just keep the 213 version. This removes 2968 bytes from the isel table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312313 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
bd19fad99b
commit
8481f03def
@ -324,12 +324,14 @@ multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, bit IsCommutable = 0,
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bit IsKCommutable = 0,
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SDNode Select = vselect> :
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SDNode Select = vselect,
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bit MaskOnly = 0> :
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AVX512_maskable_common<O, F, _, Outs,
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!con((ins _.RC:$src1), NonTiedIns),
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!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
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!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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OpcodeStr, AttSrcAsm, IntelSrcAsm,
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!if(MaskOnly, (null_frag), RHS),
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(Select _.KRCWM:$mask, RHS, _.RC:$src1),
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Select, "", NoItinerary, IsCommutable, IsKCommutable>;
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@ -337,10 +339,11 @@ multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag NonTiedIns, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, bit IsCommutable = 0,
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bit IsKCommutable = 0> :
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bit IsKCommutable = 0,
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bit MaskOnly = 0> :
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AVX512_maskable_3src<O, F, _, Outs, NonTiedIns, OpcodeStr, AttSrcAsm,
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IntelSrcAsm, RHS, IsCommutable, IsKCommutable,
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X86selects>;
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X86selects, MaskOnly>;
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multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins,
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@ -6429,7 +6432,7 @@ let Predicates = [HasAVX512] in {
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multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string Suff> {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in {
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defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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@ -6462,7 +6465,7 @@ multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string Suff> {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in
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defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
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@ -6504,11 +6507,11 @@ defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubR
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multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string Suff> {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in {
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defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
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(_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1, vselect, 1>,
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AVX512FMA3Base;
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defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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@ -6547,11 +6550,12 @@ multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string Suff> {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in
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defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
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(_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc))), 1, 1>,
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(_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc))), 1,
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1, vselect, 1>,
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AVX512FMA3Base, EVEX_B, EVEX_RC;
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}
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@ -6588,11 +6592,11 @@ defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubR
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multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string Suff> {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in {
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defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)), 1, 1>,
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(_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)), 1, 1, vselect, 1>,
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AVX512FMA3Base;
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defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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@ -6621,11 +6625,12 @@ multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, string Suff> {
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
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let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in
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defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
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(_.VT ( OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 imm:$rc))), 1, 1>,
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(_.VT ( OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 imm:$rc))), 1,
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1, vselect, 1>,
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AVX512FMA3Base, EVEX_B, EVEX_RC;
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}
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@ -6661,13 +6666,15 @@ defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddR
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defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
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// Scalar FMA
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
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dag RHS_r, dag RHS_m > {
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dag RHS_r, dag RHS_m, bit MaskOnlyReg,
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bit MaskOnlyRegInt> {
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let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
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defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3), OpcodeStr,
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"$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1>, AVX512FMA3Base;
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"$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1, MaskOnlyRegInt>,
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AVX512FMA3Base;
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defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
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@ -6675,32 +6682,33 @@ multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb, 1, 1>,
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AVX512FMA3Base, EVEX_B, EVEX_RC;
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb, 1, 1,
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MaskOnlyRegInt>, AVX512FMA3Base, EVEX_B, EVEX_RC;
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let isCodeGenOnly = 1, isCommutable = 1 in {
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def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[RHS_r]>;
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!if(MaskOnlyReg, [], [RHS_r])>;
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def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[RHS_m]>;
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}// isCodeGenOnly = 1
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}
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}// Constraints = "$src1 = $dst"
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}
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multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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string OpcodeStr, SDNode OpNode, SDNode OpNodeRnds1,
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SDNode OpNodeRnds3, X86VectorVTInfo _ , string SUFF> {
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let ExeDomain = _.ExeDomain in {
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defm NAME#213#SUFF#Z: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
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defm NAME#213#SUFF#Z: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix, _,
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// Operands for intrinsic are in 123 order to preserve passthu
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// semantics.
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3,
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(i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2,
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_.ScalarIntMemCPat:$src3, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3,
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@ -6708,10 +6716,11 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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_.FRC:$src3))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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(_.ScalarLdFrag addr:$src3))))>;
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(_.ScalarLdFrag addr:$src3)))), 0, 0>;
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defm NAME#231#SUFF#Z: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
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(_.VT (OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 FROUND_CURRENT))),
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defm NAME#231#SUFF#Z: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix, _,
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(_.VT (OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1,
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(i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds3 _.RC:$src2, _.ScalarIntMemCPat:$src3,
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_.RC:$src1, (i32 FROUND_CURRENT))),
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(_.VT ( OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1,
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@ -6719,10 +6728,11 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
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_.FRC:$src1))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
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(_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
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(_.ScalarLdFrag addr:$src3), _.FRC:$src1))), 1, 0>;
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defm NAME#132#SUFF#Z: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 FROUND_CURRENT))),
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defm NAME#132#SUFF#Z: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix, _,
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2,
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(i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.ScalarIntMemCPat:$src3,
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_.RC:$src2, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2,
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@ -6730,7 +6740,7 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
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_.FRC:$src2))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
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(_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
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(_.ScalarLdFrag addr:$src3), _.FRC:$src2))), 1, 1>;
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}
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}
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